mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
952e7760bf
The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese <sr@denx.de>
412 lines
10 KiB
C
412 lines
10 KiB
C
/*
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* (C) Copyright 2001-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include "ar405.h"
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*cmd_boot.c*/
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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extern void lxt971_no_sleep(void);
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/* ------------------------------------------------------------------------- */
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#if 0
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#define FPGA_DEBUG
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#endif
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/* fpga configuration data - generated by bin2cc */
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const unsigned char fpgadata[] = {
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#include "fpgadata.c"
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};
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const unsigned char fpgadata_xl30[] = {
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#include "fpgadata_xl30.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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int board_early_init_f (void)
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{
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int index, len, i;
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int status;
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#ifdef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f ();
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#endif
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/*
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* Boot onboard FPGA
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*/
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/* first try 40er image */
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gd->board_type = 40;
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status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
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if (status != 0) {
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/* try xl30er image */
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gd->board_type = 30;
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status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
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if (status != 0) {
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/* booting FPGA failed */
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#ifndef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f ();
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#endif
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printf ("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf ("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf ("FPGA: %s\n", &(fpgadata[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i = 20; i > 0; i--) {
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printf ("Rebooting in %2d seconds \r", i);
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for (index = 0; index < 1000; index++)
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udelay (1000);
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}
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putc ('\n');
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do_reset (NULL, 0, 0, NULL);
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}
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}
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */
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mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
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mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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int index;
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int len;
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char str[64];
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int i = getenv_r ("serial#", str, sizeof (str));
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const unsigned char *fpga;
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming AR405");
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} else {
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puts(str);
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}
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puts ("\nFPGA: ");
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/* display infos on fpgaimage */
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if (gd->board_type == 30) {
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fpga = fpgadata_xl30;
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} else {
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fpga = fpgadata;
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}
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpga[index];
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printf ("%s ", &(fpga[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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return 0;
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}
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#if 1 /* test-only: some internal test routines... */
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#define DIGEN ((void *)0xf03000b4) /* u8 */
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#define DIGOUT ((void *)0xf03000b0) /* u16 */
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#define DIGIN ((void *)0xf03000a0) /* u16 */
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/*
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* Some test routines
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*/
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int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int i;
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int k;
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int start;
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int end;
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if (argc != 3) {
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puts("Usage: digtest n_start n_end (digtest 0 7)\n");
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return 0;
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}
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start = simple_strtol (argv[1], NULL, 10);
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end = simple_strtol (argv[2], NULL, 10);
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/*
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* Enable digital outputs
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*/
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out_8(DIGEN, 0x08);
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printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
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start, end);
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/*
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* Set outputs one by one
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*/
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for (;;) {
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for (i=start; i<=end; i++) {
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out_be16(DIGOUT, 0x0001 << i);
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for (k=0; k<200; k++)
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udelay(1000);
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if (in_be16(DIGIN) != (0x0001 << i)) {
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printf("ERROR: OUT=0x%04X, IN=0x%04X\n",
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0x0001 << i, in_be16(DIGIN));
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return 0;
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}
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/* Abort if ctrl-c was pressed */
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if (ctrlc()) {
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puts("\nAbort\n");
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return 0;
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}
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}
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}
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return 0;
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}
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U_BOOT_CMD(
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digtest, 3, 1, do_digtest,
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"Test digital in-/output",
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""
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);
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#define ERROR_DELTA 256
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struct io {
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short val;
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short dummy;
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};
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int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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short val;
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int i;
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int volt;
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struct io *out;
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struct io *in;
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out = (struct io *)0xf0300090;
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in = (struct io *)0xf0300000;
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i = simple_strtol (argv[1], NULL, 10);
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volt = 0;
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printf("Setting Channel %d to %dV...\n", i, volt);
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out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
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udelay(10000);
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val = in_be16((void *)&(in[i*2].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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val = in_be16((void *)&(in[i*2+1].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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volt = 5;
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printf("Setting Channel %d to %dV...\n", i, volt);
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out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
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udelay(10000);
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val = in_be16((void *)&(in[i*2].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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val = in_be16((void *)&(in[i*2+1].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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volt = 10;
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printf("Setting Channel %d to %dV...\n", i, volt);
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out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
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udelay(10000);
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val = in_be16((void *)&(in[i*2].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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val = in_be16((void *)&(in[i*2+1].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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printf("Channel %d OK!\n", i);
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return 0;
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}
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U_BOOT_CMD(
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anatest, 2, 1, do_anatest,
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"Test analog in-/output",
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""
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);
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int counter = 0;
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void cyclicInt(void *ptr)
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{
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out_be16((void *)0xf03000e8, 0x0800); /* ack int */
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counter++;
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}
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int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong *incin;
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int i;
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incin = (ulong *)0xf0300040;
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/*
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* Clear inc counter
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*/
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out_be32((void *)&incin[0], 0);
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out_be32((void *)&incin[1], 0);
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out_be32((void *)&incin[2], 0);
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out_be32((void *)&incin[3], 0);
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incin = (ulong *)0xf0300050;
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/*
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* Inc a little
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*/
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for (i=0; i<10000; i++) {
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switch (i & 0x03) {
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case 0:
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out_8(DIGEN, 0x02);
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break;
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case 1:
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out_8(DIGEN, 0x03);
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break;
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case 2:
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out_8(DIGEN, 0x01);
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break;
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case 3:
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out_8(DIGEN, 0x00);
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break;
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}
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udelay(10);
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}
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printf("Inc 0 = %d\n", in_be32((void *)&incin[0]));
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printf("Inc 1 = %d\n", in_be32((void *)&incin[1]));
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printf("Inc 2 = %d\n", in_be32((void *)&incin[2]));
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printf("Inc 3 = %d\n", in_be32((void *)&incin[3]));
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out_be16((void *)0xf03000e0, 0x0c80-1); /* set counter */
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out_be16((void *)0xf03000ec,
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in_be16((void *)0xf03000ec) | 0x0800); /* enable int */
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irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
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printf("counter=%d\n", counter);
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return 0;
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}
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U_BOOT_CMD(
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inctest, 3, 1, do_inctest,
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"Test incremental encoder inputs",
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""
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);
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#endif
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