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0d92f2141a
Fix the MMU mapping for A8K device family: - Separate A7K and A8K memory mappings - Fix memory regions by including IO mapping for all 3 PCIe interfaces existing on each connected CP110 controller Add A8K memory mapping documentation with all regions configured by Marvell ATF. Change-Id: I9c930569b1853900f5fba2d5db319b092cc7a2a6 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> |
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cache_llc.S | ||
cpu.c | ||
Makefile |