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https://github.com/AsahiLinux/u-boot
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07e82cb2e2
for the SIUMCR and BCR Register.
Fix the calculation for the EEprom Size
Signed-off-by: Heiko Schocher <hs@denx.de>
292 lines
7.4 KiB
C
292 lines
7.4 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8260.h>
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#include <asm/cpm_8260.h>
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#include <ioports.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
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extern unsigned long board_get_cpu_clk_f (void);
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#endif
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static void config_8260_ioports (volatile immap_t * immr)
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{
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int portnum;
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for (portnum = 0; portnum < 4; portnum++) {
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uint pmsk = 0,
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ppar = 0,
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psor = 0,
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pdir = 0,
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podr = 0,
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pdat = 0;
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iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
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iop_conf_t *eiopc = iopc + 32;
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uint msk = 1;
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/*
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* NOTE:
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* index 0 refers to pin 31,
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* index 31 refers to pin 0
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*/
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while (iopc < eiopc) {
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if (iopc->conf) {
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pmsk |= msk;
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if (iopc->ppar)
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ppar |= msk;
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if (iopc->psor)
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psor |= msk;
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if (iopc->pdir)
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pdir |= msk;
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if (iopc->podr)
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podr |= msk;
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if (iopc->pdat)
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pdat |= msk;
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}
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msk <<= 1;
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iopc++;
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}
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if (pmsk != 0) {
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volatile ioport_t *iop = ioport_addr (immr, portnum);
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uint tpmsk = ~pmsk;
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/*
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* the (somewhat confused) paragraph at the
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* bottom of page 35-5 warns that there might
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* be "unknown behaviour" when programming
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* PSORx and PDIRx, if PPARx = 1, so I
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* decided this meant I had to disable the
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* dedicated function first, and enable it
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* last.
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*/
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iop->ppar &= tpmsk;
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iop->psor = (iop->psor & tpmsk) | psor;
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iop->podr = (iop->podr & tpmsk) | podr;
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iop->pdat = (iop->pdat & tpmsk) | pdat;
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iop->pdir = (iop->pdir & tpmsk) | pdir;
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iop->ppar |= ppar;
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}
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}
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}
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#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f (volatile immap_t * immr)
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{
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#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
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uint sccr;
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#endif
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#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
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unsigned long cpu_clk;
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#endif
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volatile memctl8260_t *memctl = &immr->im_memctl;
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extern void m8260_cpm_reset (void);
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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/* RSR - Reset Status Register - clear all status (5-4) */
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gd->reset_status = immr->im_clkrst.car_rsr;
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immr->im_clkrst.car_rsr = RSR_ALLBITS;
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/* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
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immr->im_clkrst.car_rmr = CFG_RMR;
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/* BCR - Bus Configuration Register (4-25) */
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#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE)
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if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
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immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_60x, 0x80000010);
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} else {
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immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_SINGLE, 0x80000010);
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}
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#else
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immr->im_siu_conf.sc_bcr = CFG_BCR;
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#endif
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/* SIUMCR - contains debug pin configuration (4-31) */
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#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH)
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cpu_clk = board_get_cpu_clk_f ();
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if (cpu_clk >= 100000000) {
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immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_HIGH, 0x9f3cc000);
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} else {
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immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_LOW, 0x9f3cc000);
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}
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#else
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immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
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#endif
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config_8260_ioports (immr);
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/* initialize time counter status and control register (4-40) */
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immr->im_sit.sit_tmcntsc = CFG_TMCNTSC;
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/* initialize the PIT (4-42) */
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immr->im_sit.sit_piscr = CFG_PISCR;
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#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
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/* System clock control register (9-8) */
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sccr = immr->im_clkrst.car_sccr &
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(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
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immr->im_clkrst.car_sccr = sccr |
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(CFG_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
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#endif /* !CONFIG_COGENT */
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/*
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* Memory Controller:
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*/
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/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
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* addresses - these have to be modified later when FLASH size
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* has been determined
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*/
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#if defined(CFG_OR0_REMAP)
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memctl->memc_or0 = CFG_OR0_REMAP;
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#endif
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#if defined(CFG_OR1_REMAP)
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memctl->memc_or1 = CFG_OR1_REMAP;
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#endif
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/* now restrict to preliminary range */
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/* the PS came from the HRCW, don´t change it */
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memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK);
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memctl->memc_or0 = CFG_OR0_PRELIM;
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#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
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memctl->memc_or1 = CFG_OR1_PRELIM;
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memctl->memc_br1 = CFG_BR1_PRELIM;
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#endif
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#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
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memctl->memc_or2 = CFG_OR2_PRELIM;
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memctl->memc_br2 = CFG_BR2_PRELIM;
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#endif
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#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
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memctl->memc_or3 = CFG_OR3_PRELIM;
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memctl->memc_br3 = CFG_BR3_PRELIM;
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#endif
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#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
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memctl->memc_or4 = CFG_OR4_PRELIM;
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memctl->memc_br4 = CFG_BR4_PRELIM;
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#endif
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#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
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memctl->memc_or5 = CFG_OR5_PRELIM;
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memctl->memc_br5 = CFG_BR5_PRELIM;
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#endif
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#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
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memctl->memc_or6 = CFG_OR6_PRELIM;
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memctl->memc_br6 = CFG_BR6_PRELIM;
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#endif
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#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
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memctl->memc_or7 = CFG_OR7_PRELIM;
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memctl->memc_br7 = CFG_BR7_PRELIM;
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#endif
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#if defined(CFG_BR8_PRELIM) && defined(CFG_OR8_PRELIM)
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memctl->memc_or8 = CFG_OR8_PRELIM;
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memctl->memc_br8 = CFG_BR8_PRELIM;
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#endif
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#if defined(CFG_BR9_PRELIM) && defined(CFG_OR9_PRELIM)
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memctl->memc_or9 = CFG_OR9_PRELIM;
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memctl->memc_br9 = CFG_BR9_PRELIM;
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#endif
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#if defined(CFG_BR10_PRELIM) && defined(CFG_OR10_PRELIM)
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memctl->memc_or10 = CFG_OR10_PRELIM;
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memctl->memc_br10 = CFG_BR10_PRELIM;
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#endif
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#if defined(CFG_BR11_PRELIM) && defined(CFG_OR11_PRELIM)
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memctl->memc_or11 = CFG_OR11_PRELIM;
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memctl->memc_br11 = CFG_BR11_PRELIM;
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#endif
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m8260_cpm_reset ();
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}
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/*
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* initialize higher level parts of CPU like time base and timers
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*/
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int cpu_init_r (void)
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{
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volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base;
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immr->im_cpm.cp_rccr = CFG_RCCR;
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return (0);
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}
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/*
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* print out the reason for the reset
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*/
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int prt_8260_rsr (void)
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{
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static struct {
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ulong mask;
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char *desc;
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} bits[] = {
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{
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RSR_JTRS, "JTAG"}, {
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RSR_CSRS, "Check Stop"}, {
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RSR_SWRS, "Software Watchdog"}, {
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RSR_BMRS, "Bus Monitor"}, {
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RSR_ESRS, "External Soft"}, {
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RSR_EHRS, "External Hard"}
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};
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static int n = sizeof bits / sizeof bits[0];
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ulong rsr = gd->reset_status;
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int i;
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char *sep;
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puts (CPU_ID_STR " Reset Status:");
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sep = " ";
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for (i = 0; i < n; i++)
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if (rsr & bits[i].mask) {
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printf ("%s%s", sep, bits[i].desc);
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sep = ", ";
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}
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puts ("\n\n");
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return (0);
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}
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