Ley Foon Tan f62782fb29 cache: l2x0: Fix write to incorrect shared-override bit ... The existing code write bit-0 for shared attribute override enable bit. It should be bit-22 based on cache controller specification [1]. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>		2020-04-24 16:40:09 -04:00
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cache-l2x0.c	cache: l2x0: Fix write to incorrect shared-override bit	2020-04-24 16:40:09 -04:00
cache-ncore.c	common: Move hang() to the same header as panic()	2020-01-17 17:53:40 -05:00
cache-uclass.c	dm: cache: Add enable and disable ops for cache uclass	2019-09-03 09:31:03 +08:00
cache-v5l2.c	common: Move hang() to the same header as panic()	2020-01-17 17:53:40 -05:00
Kconfig	cache: Add Arteris Ncore cache coherent unit driver	2020-01-07 14:38:33 +01:00
Makefile	cache: Add Arteris Ncore cache coherent unit driver	2020-01-07 14:38:33 +01:00
sandbox_cache.c	dm: cache: Add enable and disable ops for sandbox and test	2019-09-03 09:31:03 +08:00