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1918ff5c95
This driver provides clock and reset control for the Renesas R9A07G044L
(RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts:
* driver code which is applicable to all SoCs in the RZ/G2L family.
* static data describing the clocks and resets which are specific to the
R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter)
is used to indicate that both SoCs are supported.
clk_set_rate() and clk_get_rate() are implemented only for the clocks
that are actually used in u-boot.
The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind
function is called before the SCIF (serial port) driver is probed. This
is required so that we can de-assert the relevant reset signal during
the serial driver probe function.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
18 lines
403 B
Text
18 lines
403 B
Text
# Copyright (C) 2023 Renesas Electronics Corporation
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# SPDX-License-Identifier: GPL-2.0+
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if RZG2L
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config R9A07G044L
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bool "Renesas R9A07G044L SoC"
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imply CLK_R9A07G044
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help
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Enable support for the Renesas R9A07G044L (RZ/G2L) SoC.
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config MULTI_DTB_FIT_UNCOMPRESS_SZ
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default 0x80000 if TARGET_RZG2L_SMARC_EVK
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config MULTI_DTB_FIT_USER_DEF_ADDR
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default 0x49000000 if TARGET_RZG2L_SMARC_EVK
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endif
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