mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
0b8fa03b6d
JFFS2 speed enhancements:
- repair header CRC calculation in jffs2_1pass.c
- add eraseblock size to the partition information to skip empty
eraseblocks if we find more then 4k of free space.
- The JFFS2 scanner is now fast enough to remove the spinning wheel
so #ifdef-ed out.
- add watchdog calls in long running loops
* Patch by Philippe Robin, 22 Apr 2004:
Fix ethernet configuration for "versatile" board
* Patch by Kshitij Gupta, 21 Apr 2004:
Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards
* Patch by Steven Scholz, 24 Feb 2004:
Fix a bug in AT91RM9200 ethernet driver:
The MII interface is now initialized before accessing the PHY.
* Cleanup PCI ID's
500 lines
13 KiB
C
500 lines
13 KiB
C
/*
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* (C) Copyright 2003
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* Author : Hamid Ikdoumi (Atmel)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <at91rm9200_net.h>
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#include <net.h>
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/* ----- Ethernet Buffer definitions ----- */
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typedef struct {
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unsigned long addr, size;
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} rbf_t;
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#define RBF_ADDR 0xfffffffc
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#define RBF_OWNER (1<<0)
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#define RBF_WRAP (1<<1)
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#define RBF_BROADCAST (1<<31)
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#define RBF_MULTICAST (1<<30)
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#define RBF_UNICAST (1<<29)
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#define RBF_EXTERNAL (1<<28)
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#define RBF_UNKOWN (1<<27)
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#define RBF_SIZE 0x07ff
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#define RBF_LOCAL4 (1<<26)
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#define RBF_LOCAL3 (1<<25)
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#define RBF_LOCAL2 (1<<24)
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#define RBF_LOCAL1 (1<<23)
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/* Emac Buffers in last 512KBytes of SDRAM*/
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/* Be careful, buffer size is limited to 512KBytes !!! */
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#define RBF_FRAMEMAX 100
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/*#define RBF_FRAMEMEM 0x200000 */
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#define RBF_FRAMEMEM 0x21F80000
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#define RBF_FRAMELEN 0x600
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#define RBF_FRAMEBTD RBF_FRAMEMEM
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#define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t))
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#ifdef CONFIG_DRIVER_ETHER
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#if (CONFIG_COMMANDS & CFG_CMD_NET)
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/* structure to interface the PHY */
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AT91S_PhyOps AT91S_Dm9161Ops;
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AT91PS_PhyOps pPhyOps;
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AT91PS_EMAC p_mac;
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/*************************** Phy layer functions ************************/
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/** functions to interface the DAVICOM 10/100Mbps ethernet phy **********/
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/*
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* Name:
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* dm9161_IsPhyConnected
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* Description:
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* Reads the 2 PHY ID registers
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* Arguments:
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* p_mac - pointer to AT91S_EMAC struct
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* Return value:
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* TRUE - if id read successfully
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* FALSE- if error
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*/
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static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
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{
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unsigned short Id1, Id2;
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at91rm9200_EmacEnableMDIO (p_mac);
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at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
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at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
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at91rm9200_EmacDisableMDIO (p_mac);
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if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
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((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
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return TRUE;
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return FALSE;
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}
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/*
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* Name:
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* dm9161_GetLinkSpeed
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* Description:
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* Link parallel detection status of MAC is checked and set in the
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* MAC configuration registers
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* Arguments:
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* p_mac - pointer to MAC
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* Return value:
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* TRUE - if link status set succesfully
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* FALSE - if link status not set
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*/
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static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
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{
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unsigned short stat1, stat2;
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
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return FALSE;
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if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
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return FALSE;
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
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return FALSE;
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if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
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/*set Emac for 100BaseTX and Full Duplex */
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p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
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return TRUE;
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}
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if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
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/*set MII for 10BaseT and Full Duplex */
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p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
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~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
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| AT91C_EMAC_FD;
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return TRUE;
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}
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if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
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/*set MII for 100BaseTX and Half Duplex */
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p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
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~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
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| AT91C_EMAC_SPD;
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return TRUE;
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}
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if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
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/*set MII for 10BaseT and Half Duplex */
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p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
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return TRUE;
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}
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return FALSE;
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}
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/*
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* Name:
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* dm9161_InitPhy
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* Description:
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* MAC starts checking its link by using parallel detection and
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* Autonegotiation and the same is set in the MAC configuration registers
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* Arguments:
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* p_mac - pointer to struct AT91S_EMAC
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* Return value:
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* TRUE - if link status set succesfully
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* FALSE - if link status not set
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*/
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static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
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{
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UCHAR ret = TRUE;
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unsigned short IntValue;
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at91rm9200_EmacEnableMDIO (p_mac);
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if (!dm9161_GetLinkSpeed (p_mac)) {
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/* Try another time */
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ret = dm9161_GetLinkSpeed (p_mac);
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}
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/* Disable PHY Interrupts */
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at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
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/* clear FDX, SPD, Link, INTR masks */
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IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
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DM9161_LINK_MASK | DM9161_INTR_MASK);
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at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
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at91rm9200_EmacDisableMDIO (p_mac);
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return (ret);
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}
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/*
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* Name:
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* dm9161_AutoNegotiate
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* Description:
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* MAC Autonegotiates with the partner status of same is set in the
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* MAC configuration registers
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* Arguments:
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* dev - pointer to struct net_device
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* Return value:
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* TRUE - if link status set successfully
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* FALSE - if link status not set
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*/
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static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
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{
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unsigned short value;
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unsigned short PhyAnar;
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unsigned short PhyAnalpar;
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/* Set dm9161 control register */
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
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value |= DM9161_ISOLATE; /* Electrically isolate PHY */
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if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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/* Set the Auto_negotiation Advertisement Register */
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/* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
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PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
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DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
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if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
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return FALSE;
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/* Read the Control Register */
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
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if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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/* Restart Auto_negotiation */
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value |= DM9161_RESTART_AUTONEG;
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if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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/*check AutoNegotiate complete */
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udelay (10000);
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at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
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if (!(value & DM9161_AUTONEG_COMP))
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return FALSE;
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/* Get the AutoNeg Link partner base page */
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
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return FALSE;
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if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
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/*set MII for 100BaseTX and Full Duplex */
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p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
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return TRUE;
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}
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if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
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/*set MII for 10BaseT and Full Duplex */
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p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
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~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
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| AT91C_EMAC_FD;
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return TRUE;
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}
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return FALSE;
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}
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/*********** EMAC Phy layer Management functions *************************/
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/*
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* Name:
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* at91rm9200_EmacEnableMDIO
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* Description:
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* Enables the MDIO bit in MAC control register
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* Arguments:
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* p_mac - pointer to struct AT91S_EMAC
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* Return value:
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* none
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*/
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static void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
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{
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/* Mac CTRL reg set for MDIO enable */
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p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
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}
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/*
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* Name:
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* at91rm9200_EmacDisableMDIO
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* Description:
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* Disables the MDIO bit in MAC control register
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* Arguments:
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* p_mac - pointer to struct AT91S_EMAC
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* Return value:
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* none
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*/
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static void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
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{
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/* Mac CTRL reg set for MDIO disable */
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p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
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}
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/*
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* Name:
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* at91rm9200_EmacReadPhy
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* Description:
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* Reads data from the PHY register
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* Arguments:
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* dev - pointer to struct net_device
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* RegisterAddress - unsigned char
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* pInput - pointer to value read from register
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* Return value:
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* TRUE - if data read successfully
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*/
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static UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
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unsigned char RegisterAddress,
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unsigned short *pInput)
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{
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p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
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(AT91C_EMAC_RW_R) |
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(RegisterAddress << 18) |
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(AT91C_EMAC_CODE_802_3);
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udelay (10000);
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*pInput = (unsigned short) p_mac->EMAC_MAN;
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return TRUE;
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}
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/*
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* Name:
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* at91rm9200_EmacWritePhy
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* Description:
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* Writes data to the PHY register
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* Arguments:
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* dev - pointer to struct net_device
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* RegisterAddress - unsigned char
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* pOutput - pointer to value to be written in the register
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* Return value:
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* TRUE - if data read successfully
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*/
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static UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
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unsigned char RegisterAddress,
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unsigned short *pOutput)
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{
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p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
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AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
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(RegisterAddress << 18) | *pOutput;
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udelay (10000);
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return TRUE;
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}
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/*
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* Name:
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* at91rm92000_GetPhyInterface
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* Description:
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* Initialise the interface functions to the PHY
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* Arguments:
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* None
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* Return value:
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* None
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*/
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void at91rm92000_GetPhyInterface (void)
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{
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AT91S_Dm9161Ops.Init = dm9161_InitPhy;
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AT91S_Dm9161Ops.IsPhyConnected = dm9161_IsPhyConnected;
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AT91S_Dm9161Ops.GetLinkSpeed = dm9161_GetLinkSpeed;
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AT91S_Dm9161Ops.AutoNegotiate = dm9161_AutoNegotiate;
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pPhyOps = (AT91PS_PhyOps) & AT91S_Dm9161Ops;
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}
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rbf_t *rbfdt;
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rbf_t *rbfp;
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int eth_init (bd_t * bd)
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{
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int ret;
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int i;
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p_mac = AT91C_BASE_EMAC;
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/* PIO Disable Register */
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*AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
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AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
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AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
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AT91C_PA7_ETXCK_EREFCK;
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*AT91C_PIOB_PDR = AT91C_PB25_EF100 |
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AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
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AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
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AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
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/* Select B Register */
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*AT91C_PIOB_BSR = AT91C_PB25_EF100 | AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
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AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
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AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
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*AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
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p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
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/* Init Ehternet buffers */
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rbfdt = (rbf_t *) RBF_FRAMEBTD;
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for (i = 0; i < RBF_FRAMEMAX; i++) {
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rbfdt[i].addr = RBF_FRAMEBUF + RBF_FRAMELEN * i;
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rbfdt[i].size = 0;
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}
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rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
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rbfp = &rbfdt[0];
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p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
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| (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]);
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p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]);
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p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
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p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
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p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
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& ~AT91C_EMAC_CLK;
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#ifdef CONFIG_AT91C_USE_RMII
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p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
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#endif
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p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
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at91rm92000_GetPhyInterface ();
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if (!pPhyOps->IsPhyConnected (p_mac))
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printf ("PHY not connected!!\n\r");
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/* MII management start from here */
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if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
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if (!(ret = pPhyOps->Init (p_mac))) {
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printf ("MAC: error during MII initialization\n");
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return 0;
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}
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} else {
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printf ("No link\n\r");
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return 0;
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}
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return 0;
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}
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int eth_send (volatile void *packet, int length)
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{
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while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
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p_mac->EMAC_TAR = (long) packet;
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p_mac->EMAC_TCR = length;
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while (p_mac->EMAC_TCR & 0x7ff);
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p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
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return 0;
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}
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int eth_rx (void)
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{
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int size;
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if (!(rbfp->addr & RBF_OWNER))
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return 0;
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|
|
size = rbfp->size & RBF_SIZE;
|
|
NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
|
|
|
|
rbfp->addr &= ~RBF_OWNER;
|
|
if (rbfp->addr & RBF_WRAP)
|
|
rbfp = &rbfdt[0];
|
|
else
|
|
rbfp++;
|
|
|
|
p_mac->EMAC_RSR |= AT91C_EMAC_REC;
|
|
|
|
return size;
|
|
}
|
|
|
|
void eth_halt (void)
|
|
{
|
|
};
|
|
|
|
#if (CONFIG_COMMANDS & CFG_CMD_MII)
|
|
int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
|
|
{
|
|
at91rm9200_EmacEnableMDIO (p_mac);
|
|
at91rm9200_EmacReadPhy (p_mac, reg, value);
|
|
at91rm9200_EmacDisableMDIO (p_mac);
|
|
return 0;
|
|
}
|
|
|
|
int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
|
|
{
|
|
at91rm9200_EmacEnableMDIO (p_mac);
|
|
at91rm9200_EmacWritePhy (p_mac, reg, &value);
|
|
at91rm9200_EmacDisableMDIO (p_mac);
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
|
|
|
|
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
|
|
|
|
#endif /* CONFIG_DRIVER_ETHER */
|