mirror of
https://github.com/AsahiLinux/u-boot
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1e94b46f73
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
420 lines
9.5 KiB
C
420 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Mediatek "glue layer"
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*
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* Copyright (C) 2019-2021 by Mediatek
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* Based on the AllWinner SUNXI "glue layer" code.
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* Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
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* Copyright (C) 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <dm/root.h>
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#include <linux/delay.h>
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#include <linux/printk.h>
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#include <linux/usb/musb.h>
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#include <usb.h>
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#include "linux-compat.h"
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#include "musb_core.h"
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#include "musb_uboot.h"
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#define DBG_I(fmt, ...) \
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pr_info(fmt, ##__VA_ARGS__)
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struct mtk_musb_config {
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struct musb_hdrc_config *config;
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};
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struct mtk_musb_glue {
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struct musb_host_data mdata;
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struct clk usbpllclk;
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struct clk usbmcuclk;
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struct clk usbclk;
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struct mtk_musb_config *cfg;
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struct device dev;
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};
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#define to_mtk_musb_glue(d) container_of(d, struct mtk_musb_glue, dev)
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/******************************************************************************
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* phy settings
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******************************************************************************/
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#define USB20_PHY_BASE 0x11110800
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#define USBPHY_READ8(offset) \
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readb((void *)(USB20_PHY_BASE + (offset)))
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#define USBPHY_WRITE8(offset, value) \
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writeb(value, (void *)(USB20_PHY_BASE + (offset)))
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#define USBPHY_SET8(offset, mask) \
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USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) | (mask))
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#define USBPHY_CLR8(offset, mask) \
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USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) & (~(mask)))
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static void mt_usb_phy_poweron(void)
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{
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/*
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* switch to USB function.
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* (system register, force ip into usb mode).
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*/
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USBPHY_CLR8(0x6b, 0x04);
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USBPHY_CLR8(0x6e, 0x01);
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USBPHY_CLR8(0x21, 0x03);
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/* RG_USB20_BC11_SW_EN = 1'b0 */
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USBPHY_SET8(0x22, 0x04);
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USBPHY_CLR8(0x1a, 0x80);
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/* RG_USB20_DP_100K_EN = 1'b0 */
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/* RG_USB20_DP_100K_EN = 1'b0 */
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USBPHY_CLR8(0x22, 0x03);
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/*OTG enable*/
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USBPHY_SET8(0x20, 0x10);
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/* release force suspendm */
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USBPHY_CLR8(0x6a, 0x04);
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mdelay(800);
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/* force enter device mode */
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USBPHY_CLR8(0x6c, 0x10);
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USBPHY_SET8(0x6c, 0x2E);
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USBPHY_SET8(0x6d, 0x3E);
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}
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static void mt_usb_phy_savecurrent(void)
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{
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/*
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* switch to USB function.
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* (system register, force ip into usb mode).
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*/
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USBPHY_CLR8(0x6b, 0x04);
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USBPHY_CLR8(0x6e, 0x01);
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USBPHY_CLR8(0x21, 0x03);
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/* release force suspendm */
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USBPHY_CLR8(0x6a, 0x04);
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USBPHY_SET8(0x68, 0x04);
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/* RG_DPPULLDOWN./RG_DMPULLDOWN. */
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USBPHY_SET8(0x68, 0xc0);
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/* RG_XCVRSEL[1:0] = 2'b01 */
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USBPHY_CLR8(0x68, 0x30);
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USBPHY_SET8(0x68, 0x10);
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/* RG_TERMSEL = 1'b1 */
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USBPHY_SET8(0x68, 0x04);
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/* RG_DATAIN[3:0] = 4'b0000 */
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USBPHY_CLR8(0x69, 0x3c);
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/*
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* force_dp_pulldown, force_dm_pulldown,
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* force_xcversel, force_termsel.
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*/
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USBPHY_SET8(0x6a, 0xba);
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/* RG_USB20_BC11_SW_EN = 1'b0 */
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USBPHY_CLR8(0x1a, 0x80);
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/* RG_USB20_OTG_VBUSSCMP_EN = 1'b0 */
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USBPHY_CLR8(0x1a, 0x10);
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mdelay(800);
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USBPHY_CLR8(0x6a, 0x04);
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/* rg_usb20_pll_stable = 1 */
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//USBPHY_SET8(0x63, 0x02);
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mdelay(1);
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/* force suspendm = 1 */
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//USBPHY_SET8(0x6a, 0x04);
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}
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static void mt_usb_phy_recover(void)
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{
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/* clean PUPD_BIST_EN */
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/* PUPD_BIST_EN = 1'b0 */
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/* PMIC will use it to detect charger type */
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USBPHY_CLR8(0x1d, 0x10);
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/* force_uart_en = 1'b0 */
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USBPHY_CLR8(0x6b, 0x04);
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/* RG_UART_EN = 1'b0 */
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USBPHY_CLR8(0x6e, 0x01);
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/* force_uart_en = 1'b0 */
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USBPHY_CLR8(0x6a, 0x04);
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USBPHY_CLR8(0x21, 0x03);
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USBPHY_CLR8(0x68, 0xf4);
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/* RG_DATAIN[3:0] = 4'b0000 */
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USBPHY_CLR8(0x69, 0x3c);
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USBPHY_CLR8(0x6a, 0xba);
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/* RG_USB20_BC11_SW_EN = 1'b0 */
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USBPHY_CLR8(0x1a, 0x80);
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/* RG_USB20_OTG_VBUSSCMP_EN = 1'b1 */
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USBPHY_SET8(0x1a, 0x10);
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//HQA adjustment
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USBPHY_CLR8(0x18, 0x08);
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USBPHY_SET8(0x18, 0x06);
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mdelay(800);
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/* force enter device mode */
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//USBPHY_CLR8(0x6c, 0x10);
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//USBPHY_SET8(0x6c, 0x2E);
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//USBPHY_SET8(0x6d, 0x3E);
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/* enable VRT internal R architecture */
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/* RG_USB20_INTR_EN = 1'b1 */
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USBPHY_SET8(0x00, 0x20);
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}
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/******************************************************************************
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* MUSB Glue code
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******************************************************************************/
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static irqreturn_t mtk_musb_interrupt(int irq, void *__hci)
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{
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struct musb *musb = __hci;
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irqreturn_t retval = IRQ_NONE;
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/* read and flush interrupts */
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musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
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// last_int_usb = musb->int_usb;
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if (musb->int_usb)
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musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
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musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
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if (musb->int_tx)
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musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
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musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
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if (musb->int_rx)
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musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
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if (musb->int_usb || musb->int_tx || musb->int_rx)
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retval |= musb_interrupt(musb);
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return retval;
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}
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/* musb_core does not call enable / disable in a balanced manner <sigh> */
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static bool enabled;
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static int mtk_musb_enable(struct musb *musb)
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{
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struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller);
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DBG_I("%s():\n", __func__);
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musb_ep_select(musb->mregs, 0);
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musb_writeb(musb->mregs, MUSB_FADDR, 0);
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if (enabled)
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return 0;
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mt_usb_phy_recover();
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enabled = true;
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return 0;
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}
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static void mtk_musb_disable(struct musb *musb)
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{
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struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller);
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int ret;
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DBG_I("%s():\n", __func__);
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if (!enabled)
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return;
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mt_usb_phy_savecurrent();
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enabled = false;
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}
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static int mtk_musb_init(struct musb *musb)
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{
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struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller);
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int ret;
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DBG_I("%s():\n", __func__);
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ret = clk_enable(&glue->usbpllclk);
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if (ret) {
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dev_err(musb->controller, "failed to enable usbpll clock\n");
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return ret;
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}
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ret = clk_enable(&glue->usbmcuclk);
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if (ret) {
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dev_err(musb->controller, "failed to enable usbmcu clock\n");
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return ret;
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}
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ret = clk_enable(&glue->usbclk);
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if (ret) {
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dev_err(musb->controller, "failed to enable usb clock\n");
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return ret;
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}
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musb->isr = mtk_musb_interrupt;
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return 0;
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}
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static int mtk_musb_exit(struct musb *musb)
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{
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struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller);
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clk_disable(&glue->usbclk);
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clk_disable(&glue->usbmcuclk);
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clk_disable(&glue->usbpllclk);
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return 0;
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}
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static const struct musb_platform_ops mtk_musb_ops = {
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.init = mtk_musb_init,
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.exit = mtk_musb_exit,
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.enable = mtk_musb_enable,
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.disable = mtk_musb_disable,
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};
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/* MTK OTG supports up to 7 endpoints */
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#define MTK_MUSB_MAX_EP_NUM 8
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#define MTK_MUSB_RAM_BITS 16
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static struct musb_fifo_cfg mtk_musb_mode_cfg[] = {
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MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(6, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(6, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(7, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(7, FIFO_RX, 512),
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};
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static struct musb_hdrc_config musb_config = {
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.fifo_cfg = mtk_musb_mode_cfg,
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.fifo_cfg_size = ARRAY_SIZE(mtk_musb_mode_cfg),
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.multipoint = true,
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.dyn_fifo = true,
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.num_eps = MTK_MUSB_MAX_EP_NUM,
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.ram_bits = MTK_MUSB_RAM_BITS,
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};
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static int musb_usb_probe(struct udevice *dev)
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{
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struct mtk_musb_glue *glue = dev_get_priv(dev);
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struct musb_host_data *host = &glue->mdata;
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struct musb_hdrc_platform_data pdata;
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void *base = dev_read_addr_ptr(dev);
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int ret;
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DBG_I("%s():\n", __func__);
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#ifdef CONFIG_USB_MUSB_HOST
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struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
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#endif
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if (!base)
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return -EINVAL;
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glue->cfg = (struct mtk_musb_config *)dev_get_driver_data(dev);
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if (!glue->cfg)
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return -EINVAL;
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ret = clk_get_by_name(dev, "usbpll", &glue->usbpllclk);
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if (ret) {
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dev_err(dev, "failed to get usbpll clock\n");
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return ret;
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}
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ret = clk_get_by_name(dev, "usbmcu", &glue->usbmcuclk);
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if (ret) {
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dev_err(dev, "failed to get usbmcu clock\n");
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return ret;
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}
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ret = clk_get_by_name(dev, "usb", &glue->usbclk);
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if (ret) {
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dev_err(dev, "failed to get usb clock\n");
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return ret;
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}
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memset(&pdata, 0, sizeof(pdata));
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pdata.power = (u8)400;
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pdata.platform_ops = &mtk_musb_ops;
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pdata.config = glue->cfg->config;
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#ifdef CONFIG_USB_MUSB_HOST
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priv->desc_before_addr = true;
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pdata.mode = MUSB_HOST;
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host->host = musb_init_controller(&pdata, &glue->dev, base);
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if (!host->host)
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return -EIO;
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ret = musb_lowlevel_init(host);
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if (!ret)
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printf("MTK MUSB OTG (Host)\n");
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#else
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pdata.mode = MUSB_PERIPHERAL;
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host->host = musb_register(&pdata, &glue->dev, base);
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if (!host->host)
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return -EIO;
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printf("MTK MUSB OTG (Peripheral)\n");
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#endif
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mt_usb_phy_poweron();
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return ret;
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}
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static int musb_usb_remove(struct udevice *dev)
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{
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struct mtk_musb_glue *glue = dev_get_priv(dev);
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struct musb_host_data *host = &glue->mdata;
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musb_stop(host->host);
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free(host->host);
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host->host = NULL;
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return 0;
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}
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static const struct mtk_musb_config mt8518_cfg = {
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.config = &musb_config,
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};
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static const struct udevice_id mtk_musb_ids[] = {
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{ .compatible = "mediatek,mt8518-musb",
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.data = (ulong)&mt8518_cfg },
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{ }
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};
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U_BOOT_DRIVER(mtk_musb) = {
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.name = "mtk_musb",
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#ifdef CONFIG_USB_MUSB_HOST
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.id = UCLASS_USB,
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#else
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.id = UCLASS_USB_GADGET_GENERIC,
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#endif
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.of_match = mtk_musb_ids,
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.probe = musb_usb_probe,
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.remove = musb_usb_remove,
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#ifdef CONFIG_USB_MUSB_HOST
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.ops = &musb_usb_ops,
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#endif
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.plat_auto = sizeof(struct usb_plat),
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.priv_auto = sizeof(struct mtk_musb_glue),
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};
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