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3fc92a215b
This is a cleaned up and fixed version of a patch
mv_ddr: a380: fix SPLIT_OUT_MIX state decision
in each pattern cycle the bus state can be changed
in order to avoide it, need to back to the same bus state on each
pattern cycle
by
Moti Boskula <motib@marvell.com>
The original patch is not in Marvell's mv-ddr-marvell repository. It was
gives to us by Marvell to fix an issues with DDR training on some
boards, but it cannot be applied as is to mv-ddr-marvell, because it is
a very dirty draft patch that would certainly break other things, mainly
DDR4 training code in mv-ddr-marvell, since it changes common functions.
I have cleaned up the patch and removed stuff that seemed unnecessary
(when removed, it still fixed things). Note that I don't understand
completely what the code does exactly, since I haven't studied the DDR
training code extensively (and I suspect that no one besides some few
people in Marvell understand the code completely).
Anyway after the cleanup the patch still fixes isssues with DDR training
on the failing boards.
There was also a problem with the original patch on some of the Allied
Telesis' x530 boards, reported by Chris Packham. I have asked Chris to
send me some logs, and managed to fix it:
- if you look at the change, you'll notice that it introduces
subtraction of cur_start_win[] and cur_end_win[] members, depending on
a bit set in the current_byte_status variable
- the original patch subtracted cur_start_win[] if either
BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but
subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX)
was set
- from Chris Packham logs I discovered that the x530 board where the
original patch introduced DDR training failure, only the
BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the
patch is needed only the BYTE_SPLIT_OUT_MIX is set in the
current_byte_status variable
- this led me to the hypothesis that both cur_start_win[] and
cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is
set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at all
- this hypothesis also gains credibility when considering the commit
title ("fix SPLIT_OUT_MIX state decision")
Hopefully this will fix things without breaking anything else.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Chris Packham <judge.packham@gmail.com>
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|---|---|---|
| .. | ||
| ddr3_debug.c | ||
| ddr3_init.c | ||
| ddr3_init.h | ||
| ddr3_logging_def.h | ||
| ddr3_patterns_64bit.h | ||
| ddr3_training.c | ||
| ddr3_training_bist.c | ||
| ddr3_training_centralization.c | ||
| ddr3_training_db.c | ||
| ddr3_training_hw_algo.c | ||
| ddr3_training_hw_algo.h | ||
| ddr3_training_ip.h | ||
| ddr3_training_ip_bist.h | ||
| ddr3_training_ip_centralization.h | ||
| ddr3_training_ip_db.h | ||
| ddr3_training_ip_def.h | ||
| ddr3_training_ip_engine.c | ||
| ddr3_training_ip_engine.h | ||
| ddr3_training_ip_flow.h | ||
| ddr3_training_ip_pbs.h | ||
| ddr3_training_ip_prv_if.h | ||
| ddr3_training_leveling.c | ||
| ddr3_training_leveling.h | ||
| ddr3_training_pbs.c | ||
| ddr_ml_wrapper.h | ||
| ddr_topology_def.h | ||
| ddr_training_ip_db.h | ||
| dram_if.h | ||
| Makefile | ||
| mv_ddr_build_message.c | ||
| mv_ddr_common.c | ||
| mv_ddr_common.h | ||
| mv_ddr_plat.c | ||
| mv_ddr_plat.h | ||
| mv_ddr_regs.h | ||
| mv_ddr_spd.c | ||
| mv_ddr_spd.h | ||
| mv_ddr_sys_env_lib.c | ||
| mv_ddr_sys_env_lib.h | ||
| mv_ddr_topology.c | ||
| mv_ddr_topology.h | ||
| mv_ddr_training_db.h | ||
| seq_exec.h | ||
| xor.c | ||
| xor.h | ||
| xor_regs.h | ||