Peter Tyser d9c147f371 85xx, 86xx: Add common board_add_ram_info() ... Previously, 85xx and 86xx boards would display DRAM information on bootup such as: ... I2C: ready DRAM: Memory controller interleaving enabled: Bank interleaving! 2 GB FLASH: 256 MB ... This patch moves the printing of the DRAM controller configuration to a common board_add_ram_info() function which prints out DDR type, width, CAS latency, and ECC mode. It also makes the DDR interleaving information print out in a more sane manner: ... I2C: ready DRAM: 2 GB (DDR2, 64-bit, CL=4, ECC on) DDR Controller Interleaving Mode: bank FLASH: 256 MB ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2009-07-22 09:43:48 -05:00
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common_timing_params.h	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
ctrl_regs.c	fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT	2009-06-12 09:15:50 -05:00
ddr.h	fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT	2009-06-12 09:15:50 -05:00
ddr1_dimm_params.c	fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT	2009-06-12 09:15:50 -05:00
ddr2_dimm_params.c	fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT	2009-06-12 09:15:50 -05:00
ddr3_dimm_params.c	fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more	2009-07-01 23:21:43 -05:00
lc_common_dimm_params.c	fsl-ddr: add the DDR3 SPD infrastructure	2009-03-30 13:33:50 -05:00
main.c	85xx, 86xx: Add common board_add_ram_info()	2009-07-22 09:43:48 -05:00
Makefile	fsl-ddr: add the DDR3 SPD infrastructure	2009-03-30 13:33:50 -05:00
options.c	fsl-ddr: add the DDR3 SPD infrastructure	2009-03-30 13:33:50 -05:00
util.c	85xx, 86xx: Add common board_add_ram_info()	2009-07-22 09:43:48 -05:00