mirror of
https://github.com/AsahiLinux/u-boot
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174 lines
4 KiB
C
174 lines
4 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_ADDR_MAP
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#include <addr_map.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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void set_tlb(u8 tlb, u32 epn, u64 rpn,
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u8 perms, u8 wimge,
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u8 ts, u8 esel, u8 tsize, u8 iprot)
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{
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u32 _mas0, _mas1, _mas2, _mas3, _mas7;
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_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
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_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
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_mas2 = FSL_BOOKE_MAS2(epn, wimge);
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_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
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_mas7 = rpn >> 32;
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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#ifdef CONFIG_ENABLE_36BIT_PHYS
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mtspr(MAS7, _mas7);
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#endif
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asm volatile("isync;msync;tlbwe;isync");
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#ifdef CONFIG_ADDR_MAP
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if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
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addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
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#endif
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}
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void disable_tlb(u8 esel)
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{
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u32 _mas0, _mas1, _mas2, _mas3, _mas7;
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_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
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_mas1 = 0;
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_mas2 = 0;
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_mas3 = 0;
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_mas7 = 0;
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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#ifdef CONFIG_ENABLE_36BIT_PHYS
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mtspr(MAS7, _mas7);
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#endif
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asm volatile("isync;msync;tlbwe;isync");
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#ifdef CONFIG_ADDR_MAP
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if (gd->flags & GD_FLG_RELOC)
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addrmap_set_entry(0, 0, 0, esel);
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#endif
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}
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void invalidate_tlb(u8 tlb)
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{
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if (tlb == 0)
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mtspr(MMUCSR0, 0x4);
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if (tlb == 1)
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mtspr(MMUCSR0, 0x2);
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}
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void init_tlbs(void)
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{
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int i;
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for (i = 0; i < num_tlb_entries; i++) {
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set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn,
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tlb_table[i].perms, tlb_table[i].wimge,
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tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
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tlb_table[i].iprot);
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}
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return ;
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}
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#ifdef CONFIG_ADDR_MAP
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void init_addr_map(void)
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{
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int i;
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for (i = 0; i < num_tlb_entries; i++) {
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if (tlb_table[i].tlb == 0)
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continue;
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addrmap_set_entry(tlb_table[i].epn,
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tlb_table[i].rpn,
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(1UL << ((tlb_table[i].tsize * 2) + 10)),
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tlb_table[i].esel);
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}
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return ;
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}
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#endif
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#ifndef CONFIG_SYS_DDR_TLB_START
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#define CONFIG_SYS_DDR_TLB_START 8
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#endif
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unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
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{
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unsigned int tlb_size;
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unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
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unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
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unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
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u64 size, memsize = (u64)memsize_in_meg << 20;
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size = min(memsize, CONFIG_MAX_MEM_MAPPED);
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/* Convert (4^max) kB to (2^max) bytes */
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max_cam = max_cam * 2 + 10;
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for (; size && ram_tlb_index < 16; ram_tlb_index++) {
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u32 camsize = __ilog2_u64(size) & ~1U;
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u32 align = __ilog2(ram_tlb_address) & ~1U;
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if (align == -2) align = max_cam;
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if (camsize > align)
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camsize = align;
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if (camsize > max_cam)
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camsize = max_cam;
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tlb_size = (camsize - 10) / 2;
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set_tlb(1, ram_tlb_address, ram_tlb_address,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, ram_tlb_index, tlb_size, 1);
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size -= 1ULL << camsize;
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memsize -= 1ULL << camsize;
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ram_tlb_address += 1UL << camsize;
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}
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if (memsize)
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print_size(memsize, " left unmapped\n");
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/*
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* Confirm that the requested amount of memory was mapped.
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*/
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return memsize_in_meg;
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}
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