mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 12:45:42 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
44 lines
1.1 KiB
C
44 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
|
*/
|
|
|
|
#ifndef __ASM_ARCH_MX6SL_DDR_H__
|
|
#define __ASM_ARCH_MX6SL_DDR_H__
|
|
|
|
#ifndef CONFIG_MX6SL
|
|
#error "wrong CPU"
|
|
#endif
|
|
|
|
#define MX6_IOM_DRAM_CAS_B 0x020e0300
|
|
#define MX6_IOM_DRAM_CS0_B 0x020e0304
|
|
#define MX6_IOM_DRAM_CS1_B 0x020e0308
|
|
|
|
#define MX6_IOM_DRAM_DQM0 0x020e030c
|
|
#define MX6_IOM_DRAM_DQM1 0x020e0310
|
|
#define MX6_IOM_DRAM_DQM2 0x020e0314
|
|
#define MX6_IOM_DRAM_DQM3 0x020e0318
|
|
|
|
#define MX6_IOM_DRAM_RAS_B 0x020e031c
|
|
#define MX6_IOM_DRAM_RESET 0x020e0320
|
|
|
|
#define MX6_IOM_DRAM_SDBA0 0x020e0324
|
|
#define MX6_IOM_DRAM_SDBA1 0x020e0328
|
|
#define MX6_IOM_DRAM_SDBA2 0x020e032c
|
|
|
|
#define MX6_IOM_DRAM_SDCKE0 0x020e0330
|
|
#define MX6_IOM_DRAM_SDCKE1 0x020e0334
|
|
|
|
#define MX6_IOM_DRAM_SDCLK0_P 0x020e0338
|
|
|
|
#define MX6_IOM_DRAM_ODT0 0x020e033c
|
|
#define MX6_IOM_DRAM_ODT1 0x020e0340
|
|
|
|
#define MX6_IOM_DRAM_SDQS0_P 0x020e0344
|
|
#define MX6_IOM_DRAM_SDQS1_P 0x020e0348
|
|
#define MX6_IOM_DRAM_SDQS2_P 0x020e034c
|
|
#define MX6_IOM_DRAM_SDQS3_P 0x020e0350
|
|
|
|
#define MX6_IOM_DRAM_SDWE_B 0x020e0354
|
|
|
|
#endif /*__ASM_ARCH_MX6SL_DDR_H__ */
|