mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 22:33:18 +00:00
2c8941659d
Add initial DT support for R8A779G0 (R-Car V4H). Based on Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, update commit message]
1355 lines
39 KiB
Text
1355 lines
39 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
/*
|
|
* Device Tree Source for the R-Car V4H (R8A779G0) SoC
|
|
*
|
|
* Copyright (C) 2022 Renesas Electronics Corp.
|
|
*/
|
|
|
|
#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/power/r8a779g0-sysc.h>
|
|
|
|
/ {
|
|
compatible = "renesas,r8a779g0";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
cluster0_opp: opp-table-0 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-500000000 {
|
|
opp-hz = /bits/ 64 <500000000>;
|
|
opp-microvolt = <825000>;
|
|
clock-latency-ns = <500000>;
|
|
};
|
|
opp-1000000000 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <825000>;
|
|
clock-latency-ns = <500000>;
|
|
};
|
|
opp-1500000000 {
|
|
opp-hz = /bits/ 64 <1500000000>;
|
|
opp-microvolt = <825000>;
|
|
clock-latency-ns = <500000>;
|
|
};
|
|
opp-1700000000 {
|
|
opp-hz = /bits/ 64 <1700000000>;
|
|
opp-microvolt = <825000>;
|
|
clock-latency-ns = <500000>;
|
|
opp-suspend;
|
|
};
|
|
opp-1800000000 {
|
|
opp-hz = /bits/ 64 <1800000000>;
|
|
opp-microvolt = <880000>;
|
|
clock-latency-ns = <500000>;
|
|
turbo-mode;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&a76_0>;
|
|
};
|
|
core1 {
|
|
cpu = <&a76_1>;
|
|
};
|
|
};
|
|
|
|
cluster1 {
|
|
core0 {
|
|
cpu = <&a76_2>;
|
|
};
|
|
core1 {
|
|
cpu = <&a76_3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
a76_0: cpu@0 {
|
|
compatible = "arm,cortex-a76";
|
|
reg = <0>;
|
|
device_type = "cpu";
|
|
power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
|
|
next-level-cache = <&L3_CA76_0>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <&CPU_SLEEP_0>;
|
|
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
};
|
|
|
|
a76_1: cpu@100 {
|
|
compatible = "arm,cortex-a76";
|
|
reg = <0x100>;
|
|
device_type = "cpu";
|
|
power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
|
|
next-level-cache = <&L3_CA76_0>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <&CPU_SLEEP_0>;
|
|
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
};
|
|
|
|
a76_2: cpu@10000 {
|
|
compatible = "arm,cortex-a76";
|
|
reg = <0x10000>;
|
|
device_type = "cpu";
|
|
power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
|
|
next-level-cache = <&L3_CA76_1>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <&CPU_SLEEP_0>;
|
|
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
};
|
|
|
|
a76_3: cpu@10100 {
|
|
compatible = "arm,cortex-a76";
|
|
reg = <0x10100>;
|
|
device_type = "cpu";
|
|
power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
|
|
next-level-cache = <&L3_CA76_1>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <&CPU_SLEEP_0>;
|
|
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
};
|
|
|
|
idle-states {
|
|
entry-method = "psci";
|
|
|
|
CPU_SLEEP_0: cpu-sleep-0 {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x0010000>;
|
|
local-timer-stop;
|
|
entry-latency-us = <400>;
|
|
exit-latency-us = <500>;
|
|
min-residency-us = <4000>;
|
|
};
|
|
};
|
|
|
|
L3_CA76_0: cache-controller-0 {
|
|
compatible = "cache";
|
|
power-domains = <&sysc R8A779G0_PD_A2E0D0>;
|
|
cache-unified;
|
|
cache-level = <3>;
|
|
};
|
|
|
|
L3_CA76_1: cache-controller-1 {
|
|
compatible = "cache";
|
|
power-domains = <&sysc R8A779G0_PD_A2E0D1>;
|
|
cache-unified;
|
|
cache-level = <3>;
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
extal_clk: extal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
extalr_clk: extalr {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
pmu_a76 {
|
|
compatible = "arm,cortex-a76-pmu";
|
|
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
/* External SCIF clock - to be overridden by boards that provide it */
|
|
scif_clk: scif {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
soc: soc {
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
rwdt: watchdog@e6020000 {
|
|
compatible = "renesas,r8a779g0-wdt",
|
|
"renesas,rcar-gen4-wdt";
|
|
reg = <0 0xe6020000 0 0x0c>;
|
|
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 907>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 907>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pfc: pinctrl@e6050000 {
|
|
compatible = "renesas,pfc-r8a779g0";
|
|
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
|
|
<0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
|
|
<0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
|
|
<0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
|
|
<0 0xe6068000 0 0x16c>;
|
|
};
|
|
|
|
gpio0: gpio@e6050180 {
|
|
compatible = "renesas,gpio-r8a779g0",
|
|
"renesas,rcar-gen4-gpio";
|
|
reg = <0 0xe6050180 0 0x54>;
|
|
interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 915>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 915>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pfc 0 0 19>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio@e6050980 {
|
|
compatible = "renesas,gpio-r8a779g0",
|
|
"renesas,rcar-gen4-gpio";
|
|
reg = <0 0xe6050980 0 0x54>;
|
|
interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 915>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 915>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pfc 0 32 29>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@e6058180 {
|
|
compatible = "renesas,gpio-r8a779g0",
|
|
"renesas,rcar-gen4-gpio";
|
|
reg = <0 0xe6058180 0 0x54>;
|
|
interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 916>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 916>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pfc 0 64 20>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@e6058980 {
|
|
compatible = "renesas,gpio-r8a779g0",
|
|
"renesas,rcar-gen4-gpio";
|
|
reg = <0 0xe6058980 0 0x54>;
|
|
interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 916>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 916>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pfc 0 96 30>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@e6060180 {
|
|
compatible = "renesas,gpio-r8a779g0",
|
|
"renesas,rcar-gen4-gpio";
|
|
reg = <0 0xe6060180 0 0x54>;
|
|
interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 917>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 917>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pfc 0 128 25>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio5: gpio@e6060980 {
|
|
compatible = "renesas,gpio-r8a779g0",
|
|
"renesas,rcar-gen4-gpio";
|
|
reg = <0 0xe6060980 0 0x54>;
|
|
interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 917>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 917>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pfc 0 160 21>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio6: gpio@e6061180 {
|
|
compatible = "renesas,gpio-r8a779g0",
|
|
"renesas,rcar-gen4-gpio";
|
|
reg = <0 0xe6061180 0 0x54>;
|
|
interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 917>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 917>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pfc 0 192 21>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio7: gpio@e6061980 {
|
|
compatible = "renesas,gpio-r8a779g0",
|
|
"renesas,rcar-gen4-gpio";
|
|
reg = <0 0xe6061980 0 0x54>;
|
|
interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 917>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 917>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pfc 0 224 21>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio8: gpio@e6068180 {
|
|
compatible = "renesas,gpio-r8a779g0",
|
|
"renesas,rcar-gen4-gpio";
|
|
reg = <0 0xe6068180 0 0x54>;
|
|
interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 918>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 918>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pfc 0 256 14>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
cmt0: timer@e60f0000 {
|
|
compatible = "renesas,r8a779g0-cmt0",
|
|
"renesas,rcar-gen4-cmt0";
|
|
reg = <0 0xe60f0000 0 0x1004>;
|
|
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 910>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 910>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cmt1: timer@e6130000 {
|
|
compatible = "renesas,r8a779g0-cmt1",
|
|
"renesas,rcar-gen4-cmt1";
|
|
reg = <0 0xe6130000 0 0x1004>;
|
|
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 911>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 911>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cmt2: timer@e6140000 {
|
|
compatible = "renesas,r8a779g0-cmt1",
|
|
"renesas,rcar-gen4-cmt1";
|
|
reg = <0 0xe6140000 0 0x1004>;
|
|
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 912>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 912>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cmt3: timer@e6148000 {
|
|
compatible = "renesas,r8a779g0-cmt1",
|
|
"renesas,rcar-gen4-cmt1";
|
|
reg = <0 0xe6148000 0 0x1004>;
|
|
interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 913>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 913>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpg: clock-controller@e6150000 {
|
|
compatible = "renesas,r8a779g0-cpg-mssr";
|
|
reg = <0 0xe6150000 0 0x4000>;
|
|
clocks = <&extal_clk>, <&extalr_clk>;
|
|
clock-names = "extal", "extalr";
|
|
#clock-cells = <2>;
|
|
#power-domain-cells = <0>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
rst: reset-controller@e6160000 {
|
|
compatible = "renesas,r8a779g0-rst";
|
|
reg = <0 0xe6160000 0 0x4000>;
|
|
};
|
|
|
|
sysc: system-controller@e6180000 {
|
|
compatible = "renesas,r8a779g0-sysc";
|
|
reg = <0 0xe6180000 0 0x4000>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
intc_ex: interrupt-controller@e61c0000 {
|
|
compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc";
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
reg = <0 0xe61c0000 0 0x200>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 611>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 611>;
|
|
};
|
|
|
|
tmu0: timer@e61e0000 {
|
|
compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
|
|
reg = <0 0xe61e0000 0 0x30>;
|
|
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 713>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 713>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu1: timer@e6fc0000 {
|
|
compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
|
|
reg = <0 0xe6fc0000 0 0x30>;
|
|
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 714>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 714>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu2: timer@e6fd0000 {
|
|
compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
|
|
reg = <0 0xe6fd0000 0 0x30>;
|
|
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 715>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 715>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu3: timer@e6fe0000 {
|
|
compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
|
|
reg = <0 0xe6fe0000 0 0x30>;
|
|
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 716>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 716>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu4: timer@ffc00000 {
|
|
compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
|
|
reg = <0 0xffc00000 0 0x30>;
|
|
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 717>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 717>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@e6500000 {
|
|
compatible = "renesas,i2c-r8a779g0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe6500000 0 0x40>;
|
|
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 518>;
|
|
dmas = <&dmac0 0x91>, <&dmac0 0x90>,
|
|
<&dmac1 0x91>, <&dmac1 0x90>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 518>;
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@e6508000 {
|
|
compatible = "renesas,i2c-r8a779g0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe6508000 0 0x40>;
|
|
interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 519>;
|
|
dmas = <&dmac0 0x93>, <&dmac0 0x92>,
|
|
<&dmac1 0x93>, <&dmac1 0x92>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 519>;
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@e6510000 {
|
|
compatible = "renesas,i2c-r8a779g0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe6510000 0 0x40>;
|
|
interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 520>;
|
|
dmas = <&dmac0 0x95>, <&dmac0 0x94>,
|
|
<&dmac1 0x95>, <&dmac1 0x94>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 520>;
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@e66d0000 {
|
|
compatible = "renesas,i2c-r8a779g0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe66d0000 0 0x40>;
|
|
interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 521>;
|
|
dmas = <&dmac0 0x97>, <&dmac0 0x96>,
|
|
<&dmac1 0x97>, <&dmac1 0x96>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 521>;
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@e66d8000 {
|
|
compatible = "renesas,i2c-r8a779g0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe66d8000 0 0x40>;
|
|
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 522>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
dmas = <&dmac0 0x99>, <&dmac0 0x98>,
|
|
<&dmac1 0x99>, <&dmac1 0x98>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 522>;
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@e66e0000 {
|
|
compatible = "renesas,i2c-r8a779g0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe66e0000 0 0x40>;
|
|
interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
|
|
<&dmac1 0x9b>, <&dmac1 0x9a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif0: serial@e6540000 {
|
|
compatible = "renesas,hscif-r8a779g0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe6540000 0 0x60>;
|
|
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 514>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x31>, <&dmac0 0x30>,
|
|
<&dmac1 0x31>, <&dmac1 0x30>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 514>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif1: serial@e6550000 {
|
|
compatible = "renesas,hscif-r8a779g0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe6550000 0 0x60>;
|
|
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 515>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x33>, <&dmac0 0x32>,
|
|
<&dmac1 0x33>, <&dmac1 0x32>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 515>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif2: serial@e6560000 {
|
|
compatible = "renesas,hscif-r8a779g0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe6560000 0 0x60>;
|
|
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 516>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x35>, <&dmac0 0x34>,
|
|
<&dmac1 0x35>, <&dmac1 0x34>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 516>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif3: serial@e66a0000 {
|
|
compatible = "renesas,hscif-r8a779g0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe66a0000 0 0x60>;
|
|
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 517>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x37>, <&dmac0 0x36>,
|
|
<&dmac1 0x37>, <&dmac1 0x36>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 517>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb0: ethernet@e6800000 {
|
|
compatible = "renesas,etheravb-r8a779g0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6800000 0 0x800>;
|
|
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
|
|
"ch5", "ch6", "ch7", "ch8", "ch9",
|
|
"ch10", "ch11", "ch12", "ch13",
|
|
"ch14", "ch15", "ch16", "ch17",
|
|
"ch18", "ch19", "ch20", "ch21",
|
|
"ch22", "ch23", "ch24";
|
|
clocks = <&cpg CPG_MOD 211>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 211>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb1: ethernet@e6810000 {
|
|
compatible = "renesas,etheravb-r8a779g0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6810000 0 0x800>;
|
|
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
|
|
"ch5", "ch6", "ch7", "ch8", "ch9",
|
|
"ch10", "ch11", "ch12", "ch13",
|
|
"ch14", "ch15", "ch16", "ch17",
|
|
"ch18", "ch19", "ch20", "ch21",
|
|
"ch22", "ch23", "ch24";
|
|
clocks = <&cpg CPG_MOD 212>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 212>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb2: ethernet@e6820000 {
|
|
compatible = "renesas,etheravb-r8a779g0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6820000 0 0x1000>;
|
|
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
|
|
"ch5", "ch6", "ch7", "ch8", "ch9",
|
|
"ch10", "ch11", "ch12", "ch13",
|
|
"ch14", "ch15", "ch16", "ch17",
|
|
"ch18", "ch19", "ch20", "ch21",
|
|
"ch22", "ch23", "ch24";
|
|
clocks = <&cpg CPG_MOD 213>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 213>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@e6e30000 {
|
|
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e30000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@e6e31000 {
|
|
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e31000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@e6e32000 {
|
|
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e32000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@e6e33000 {
|
|
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e33000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@e6e34000 {
|
|
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e34000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm5: pwm@e6e35000 {
|
|
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e35000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm6: pwm@e6e36000 {
|
|
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e36000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm7: pwm@e6e37000 {
|
|
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e37000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm8: pwm@e6e38000 {
|
|
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e38000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm9: pwm@e6e39000 {
|
|
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e39000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a779g0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 702>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x51>, <&dmac0 0x50>,
|
|
<&dmac1 0x51>, <&dmac1 0x50>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 702>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a779g0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x53>, <&dmac0 0x52>,
|
|
<&dmac1 0x53>, <&dmac1 0x52>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 703>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6c50000 {
|
|
compatible = "renesas,scif-r8a779g0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6c50000 0 64>;
|
|
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 704>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x57>, <&dmac0 0x56>,
|
|
<&dmac1 0x57>, <&dmac1 0x56>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 704>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6c40000 {
|
|
compatible = "renesas,scif-r8a779g0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6c40000 0 64>;
|
|
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 705>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x59>, <&dmac0 0x58>,
|
|
<&dmac1 0x59>, <&dmac1 0x58>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 705>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tpu: pwm@e6e80000 {
|
|
compatible = "renesas,tpu-r8a779g0", "renesas,tpu";
|
|
reg = <0 0xe6e80000 0 0x148>;
|
|
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 718>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 718>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e90000 {
|
|
compatible = "renesas,msiof-r8a779g0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6e90000 0 0x0064>;
|
|
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 618>;
|
|
dmas = <&dmac0 0x41>, <&dmac0 0x40>,
|
|
<&dmac1 0x41>, <&dmac1 0x40>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 618>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6ea0000 {
|
|
compatible = "renesas,msiof-r8a779g0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6ea0000 0 0x0064>;
|
|
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 619>;
|
|
dmas = <&dmac0 0x43>, <&dmac0 0x42>,
|
|
<&dmac1 0x43>, <&dmac1 0x42>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 619>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof2: spi@e6c00000 {
|
|
compatible = "renesas,msiof-r8a779g0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c00000 0 0x0064>;
|
|
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 620>;
|
|
dmas = <&dmac0 0x45>, <&dmac0 0x44>,
|
|
<&dmac1 0x45>, <&dmac1 0x44>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 620>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof3: spi@e6c10000 {
|
|
compatible = "renesas,msiof-r8a779g0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c10000 0 0x0064>;
|
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 621>;
|
|
dmas = <&dmac0 0x47>, <&dmac0 0x46>,
|
|
<&dmac1 0x47>, <&dmac1 0x46>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 621>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof4: spi@e6c20000 {
|
|
compatible = "renesas,msiof-r8a779g0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c20000 0 0x0064>;
|
|
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 622>;
|
|
dmas = <&dmac0 0x49>, <&dmac0 0x48>,
|
|
<&dmac1 0x49>, <&dmac1 0x48>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 622>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof5: spi@e6c28000 {
|
|
compatible = "renesas,msiof-r8a779g0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c28000 0 0x0064>;
|
|
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 623>;
|
|
dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
|
|
<&dmac1 0x4b>, <&dmac1 0x4a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 623>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dmac0: dma-controller@e7350000 {
|
|
compatible = "renesas,dmac-r8a779g0",
|
|
"renesas,rcar-gen4-dmac";
|
|
reg = <0 0xe7350000 0 0x1000>,
|
|
<0 0xe7300000 0 0x10000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3", "ch4",
|
|
"ch5", "ch6", "ch7", "ch8", "ch9",
|
|
"ch10", "ch11", "ch12", "ch13",
|
|
"ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD 709>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 709>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
};
|
|
|
|
dmac1: dma-controller@e7351000 {
|
|
compatible = "renesas,dmac-r8a779g0",
|
|
"renesas,rcar-gen4-dmac";
|
|
reg = <0 0xe7351000 0 0x1000>,
|
|
<0 0xe7310000 0 0x10000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3", "ch4",
|
|
"ch5", "ch6", "ch7", "ch8", "ch9",
|
|
"ch10", "ch11", "ch12", "ch13",
|
|
"ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD 710>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 710>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
};
|
|
|
|
mmc0: mmc@ee140000 {
|
|
compatible = "renesas,sdhi-r8a779g0",
|
|
"renesas,rcar-gen4-sdhi";
|
|
reg = <0 0xee140000 0 0x2000>;
|
|
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 706>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_SD0H>;
|
|
clock-names = "core", "clkh";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 706>;
|
|
max-frequency = <200000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rpc: spi@ee200000 {
|
|
compatible = "renesas,r8a779g0-rpc-if",
|
|
"renesas,rcar-gen4-rpc-if";
|
|
reg = <0 0xee200000 0 0x200>,
|
|
<0 0x08000000 0 0x04000000>,
|
|
<0 0xee208000 0 0x100>;
|
|
reg-names = "regs", "dirmap", "wbuf";
|
|
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 629>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 629>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@f1000000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x0 0xf1000000 0 0x20000>,
|
|
<0x0 0xf1060000 0 0x110000>;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
fcpvd0: fcp@fea10000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfea10000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 508>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 508>;
|
|
};
|
|
|
|
fcpvd1: fcp@fea11000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfea11000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 509>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 509>;
|
|
};
|
|
|
|
vspd0: vsp@fea20000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfea20000 0 0x7000>;
|
|
interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 830>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 830>;
|
|
|
|
renesas,fcp = <&fcpvd0>;
|
|
};
|
|
|
|
vspd1: vsp@fea28000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfea28000 0 0x7000>;
|
|
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 831>;
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 831>;
|
|
|
|
renesas,fcp = <&fcpvd1>;
|
|
};
|
|
|
|
du: display@feb00000 {
|
|
compatible = "renesas,du-r8a779g0";
|
|
reg = <0 0xfeb00000 0 0x40000>;
|
|
interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 411>;
|
|
clock-names = "du.0";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 411>;
|
|
reset-names = "du.0";
|
|
renesas,vsps = <&vspd0 0>, <&vspd1 0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
du_out_dsi0: endpoint {
|
|
remote-endpoint = <&dsi0_in>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
du_out_dsi1: endpoint {
|
|
remote-endpoint = <&dsi1_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dsi0: dsi-encoder@fed80000 {
|
|
compatible = "renesas,r8a779g0-dsi-csi2-tx";
|
|
reg = <0 0xfed80000 0 0x10000>;
|
|
clocks = <&cpg CPG_MOD 415>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
|
|
clock-names = "fck", "dsi", "pll";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 415>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
dsi0_in: endpoint {
|
|
remote-endpoint = <&du_out_dsi0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dsi1: dsi-encoder@fed90000 {
|
|
compatible = "renesas,r8a779g0-dsi-csi2-tx";
|
|
reg = <0 0xfed90000 0 0x10000>;
|
|
clocks = <&cpg CPG_MOD 416>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
|
|
<&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
|
|
clock-names = "fck", "dsi", "pll";
|
|
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 416>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
dsi1_in: endpoint {
|
|
remote-endpoint = <&du_out_dsi1>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
prr: chipid@fff00044 {
|
|
compatible = "renesas,prr";
|
|
reg = <0 0xfff00044 0 4>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|