u-boot/arch/arm/mach-stm32mp
Patrick Delaunay dc7e5f190d arm: stm32mp: activate data cache on DDR in SPL
Activate cache on DDR to improve the accesses to DDR used by SPL:
- CONFIG_SPL_BSS_START_ADDR
- CONFIG_SYS_SPL_MALLOC_START

Cache is configured only when DDR is fully initialized,
to avoid speculative access and issue in get_ram_size().
Data cache is deactivated at the end of SPL, to flush the data cache
and the TLB.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
..
cmd_stm32prog stm32mp: stm32prog: add support of RAM target 2020-05-14 09:02:12 +02:00
include/mach stm32mp: stm32prog: adapt the MTD partitions 2020-05-14 09:02:12 +02:00
boot_params.c board: stm32mp1: use FDT address provided by TF-A at boot time 2020-05-14 09:02:12 +02:00
bsec.c configs: stm32mp1: replace STM32MP1_TRUSTED by TFABOOT 2020-04-15 09:08:37 +02:00
cmd_stm32key.c stm32mp1: key: add stm32key command 2019-07-12 11:18:53 +02:00
config.mk stm32mp1: add trusted boot with TF-A 2019-04-12 16:09:13 +02:00
cpu.c arm: stm32mp: activate data cache in SPL and before relocation 2020-05-14 09:02:12 +02:00
dram_init.c board: stm32mp1: reserve memory for OP-TEE in device tree 2020-05-14 09:02:12 +02:00
fdt.c stm32mp1: dynamically detect op-tee presence 2020-05-14 09:02:12 +02:00
Kconfig arm: stm32mp: remove dependency for STM32KEY 2020-05-14 09:02:12 +02:00
Makefile stm32mp: add the command stm32prog 2020-05-14 09:02:12 +02:00
psci.c stm32mp: psci: set cntfrq register of cpu on 2020-03-24 14:17:38 +01:00
pwr_regulator.c stm32mp1: pwr: use the last binding for pwr 2020-02-13 17:26:22 +01:00
spl.c arm: stm32mp: activate data cache on DDR in SPL 2020-05-14 09:02:12 +02:00
syscon.c stm32mp1: pwr: use the last binding for pwr 2020-02-13 17:26:22 +01:00