mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
c45568cc4e
This converts the following to Kconfig: CONFIG_SYS_BOOTM_LEN As part of this, rework error handling in boot/bootm.c so that we pass the buffer size to handle_decomp_error as CONFIG_SYS_BOOTM_LEN will not be available to host tools but we do know the size that we passed to malloc(). Cc: Soeren Moch <smoch@web.de> Signed-off-by: Tom Rini <trini@konsulko.com>
70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright 2018 NXP
|
|
*/
|
|
|
|
#ifndef __IMX8M_EVK_H
|
|
#define __IMX8M_EVK_H
|
|
|
|
#include <linux/sizes.h>
|
|
#include <linux/stringify.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
|
|
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
|
|
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
|
|
|
|
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
|
|
#define CONFIG_MALLOC_F_ADDR 0x182000
|
|
/* For RAW image gives a error info not panic */
|
|
|
|
#define CONFIG_POWER_PFUZE100
|
|
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
|
#endif
|
|
|
|
/* ENET Config */
|
|
/* ENET1 */
|
|
#if defined(CONFIG_CMD_NET)
|
|
#define CONFIG_FEC_MXC_PHYADDR 0
|
|
#endif
|
|
|
|
#define BOOT_TARGET_DEVICES(func) \
|
|
func(MMC, mmc, 0) \
|
|
func(MMC, mmc, 1) \
|
|
func(DHCP, dhcp, na)
|
|
|
|
#include <config_distro_bootcmd.h>
|
|
|
|
/* Initial environment variables */
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
BOOTENV \
|
|
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
|
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
|
"image=Image\0" \
|
|
"console=ttymxc0,115200\0" \
|
|
"fdt_addr_r=0x43000000\0" \
|
|
"boot_fdt=try\0" \
|
|
"fdtfile=imx8mq-evk.dtb\0" \
|
|
"initrd_addr=0x43800000\0" \
|
|
"bootm_size=0x10000000\0" \
|
|
"mmcpart=1\0" \
|
|
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
|
|
|
|
/* Link Definitions */
|
|
|
|
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
|
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
|
|
|
|
|
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
|
#define PHYS_SDRAM 0x40000000
|
|
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
|
|
|
|
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
|
|
|
|
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
|
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
|
|
|
#endif
|