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https://github.com/AsahiLinux/u-boot
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The SG_* macros represent the address of SoC-glue registers. For a planned new SoC, its base address will be changed. Turn the SG_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
40 lines
1.7 KiB
C
40 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <spl.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include "../sg-regs.h"
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#include "boot-device.h"
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const struct uniphier_boot_device uniphier_pxs3_boot_device_table[] = {
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
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{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
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{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"},
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{BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"},
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{BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"},
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{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
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{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5, BBM Last Page)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5, BBM Last Page)"},
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};
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const unsigned uniphier_pxs3_boot_device_count =
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ARRAY_SIZE(uniphier_pxs3_boot_device_table);
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int uniphier_pxs3_boot_device_is_usb(u32 pinmon)
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{
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return !!(readl(sg_base + SG_PINMON2) & BIT(31));
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}
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