mirror of
https://github.com/AsahiLinux/u-boot
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f31fa99a9e
Use this new name to be consistent with the rest of U-Boot, which talks about 'plat' for the platform data, which is what this file holds. Signed-off-by: Simon Glass <sjg@chromium.org>
444 lines
16 KiB
C
444 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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* Synced from Linux v4.19
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*/
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#ifndef __LINUX_MTD_SPI_NOR_H
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#define __LINUX_MTD_SPI_NOR_H
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#include <linux/bitops.h>
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#include <linux/mtd/cfi.h>
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#include <linux/mtd/mtd.h>
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/*
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* Manufacturer IDs
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*
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* The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
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* Sometimes these are the same as CFI IDs, but sometimes they aren't.
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*/
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#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
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#define SNOR_MFR_GIGADEVICE 0xc8
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#define SNOR_MFR_INTEL CFI_MFR_INTEL
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#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
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#define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
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#define SNOR_MFR_ISSI CFI_MFR_PMC
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#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
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#define SNOR_MFR_SPANSION CFI_MFR_AMD
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#define SNOR_MFR_SST CFI_MFR_SST
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#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
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/*
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* Note on opcode nomenclature: some opcodes have a format like
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* SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
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* of I/O lines used for the opcode, address, and data (respectively). The
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* FUNCTION has an optional suffix of '4', to represent an opcode which
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* requires a 4-byte (32-bit) address.
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*/
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/* Flash opcodes. */
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#define SPINOR_OP_WREN 0x06 /* Write enable */
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#define SPINOR_OP_RDSR 0x05 /* Read status register */
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#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
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#define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
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#define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
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#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
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#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
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#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
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#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
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#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
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#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
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#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
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#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
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#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
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#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
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#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
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#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
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#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
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#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
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#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
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#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
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#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
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#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
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#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
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#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
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#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
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#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
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#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
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/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
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#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
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#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
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#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
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#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
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#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
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#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
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#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
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#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
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#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
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#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
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#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
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#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
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#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
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#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
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/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
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#define SPINOR_OP_READ_1_1_1_DTR 0x0d
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#define SPINOR_OP_READ_1_2_2_DTR 0xbd
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#define SPINOR_OP_READ_1_4_4_DTR 0xed
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#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
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#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
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#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
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/* Used for SST flashes only. */
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#define SPINOR_OP_BP 0x02 /* Byte program */
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#define SPINOR_OP_WRDI 0x04 /* Write disable */
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#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
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/* Used for SST26* flashes only. */
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#define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
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#define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
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/* Used for S3AN flashes only */
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#define SPINOR_OP_XSE 0x50 /* Sector erase */
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#define SPINOR_OP_XPP 0x82 /* Page program */
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#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
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#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
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#define XSR_RDY BIT(7) /* Ready */
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/* Used for Macronix and Winbond flashes. */
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#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
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#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
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/* Used for Spansion flashes only. */
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#define SPINOR_OP_BRWR 0x17 /* Bank register write */
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#define SPINOR_OP_BRRD 0x16 /* Bank register read */
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#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
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/* Used for Micron flashes only. */
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#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
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#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
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/* Status Register bits. */
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#define SR_WIP BIT(0) /* Write in progress */
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#define SR_WEL BIT(1) /* Write enable latch */
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/* meaning of other SR_* bits may differ between vendors */
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#define SR_BP0 BIT(2) /* Block protect 0 */
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#define SR_BP1 BIT(3) /* Block protect 1 */
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#define SR_BP2 BIT(4) /* Block protect 2 */
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#define SR_TB BIT(5) /* Top/Bottom protect */
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#define SR_SRWD BIT(7) /* SR write protect */
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/* Spansion/Cypress specific status bits */
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#define SR_E_ERR BIT(5)
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#define SR_P_ERR BIT(6)
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#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
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/* Enhanced Volatile Configuration Register bits */
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#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
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/* Flag Status Register bits */
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#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
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#define FSR_E_ERR BIT(5) /* Erase operation status */
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#define FSR_P_ERR BIT(4) /* Program operation status */
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#define FSR_PT_ERR BIT(1) /* Protection error bit */
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/* Configuration Register bits. */
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#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
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/* Status Register 2 bits. */
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#define SR2_QUAD_EN_BIT7 BIT(7)
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/* Supported SPI protocols */
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#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
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#define SNOR_PROTO_INST_SHIFT 16
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#define SNOR_PROTO_INST(_nbits) \
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((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
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SNOR_PROTO_INST_MASK)
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#define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
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#define SNOR_PROTO_ADDR_SHIFT 8
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#define SNOR_PROTO_ADDR(_nbits) \
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((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
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SNOR_PROTO_ADDR_MASK)
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#define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
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#define SNOR_PROTO_DATA_SHIFT 0
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#define SNOR_PROTO_DATA(_nbits) \
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((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
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SNOR_PROTO_DATA_MASK)
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#define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
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#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
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(SNOR_PROTO_INST(_inst_nbits) | \
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SNOR_PROTO_ADDR(_addr_nbits) | \
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SNOR_PROTO_DATA(_data_nbits))
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#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
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(SNOR_PROTO_IS_DTR | \
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SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
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enum spi_nor_protocol {
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SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
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SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
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SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
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SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
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SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
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SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
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SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
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SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
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SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
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SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
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SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
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SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
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SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
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SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
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};
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static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
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{
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return !!(proto & SNOR_PROTO_IS_DTR);
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}
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static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
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{
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return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
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SNOR_PROTO_INST_SHIFT;
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}
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static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
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{
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return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
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SNOR_PROTO_ADDR_SHIFT;
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}
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static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
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{
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return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
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SNOR_PROTO_DATA_SHIFT;
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}
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static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
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{
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return spi_nor_get_protocol_data_nbits(proto);
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}
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#define SPI_NOR_MAX_CMD_SIZE 8
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enum spi_nor_ops {
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SPI_NOR_OPS_READ = 0,
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SPI_NOR_OPS_WRITE,
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SPI_NOR_OPS_ERASE,
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SPI_NOR_OPS_LOCK,
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SPI_NOR_OPS_UNLOCK,
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};
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enum spi_nor_option_flags {
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SNOR_F_USE_FSR = BIT(0),
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SNOR_F_HAS_SR_TB = BIT(1),
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SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
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SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
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SNOR_F_READY_XSR_RDY = BIT(4),
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SNOR_F_USE_CLSR = BIT(5),
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SNOR_F_BROKEN_RESET = BIT(6),
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};
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/**
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* struct flash_info - Forward declaration of a structure used internally by
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* spi_nor_scan()
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*/
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struct flash_info;
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/*
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* TODO: Remove, once all users of spi_flash interface are moved to MTD
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*
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struct spi_flash {
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* Defined below (keep this text to enable searching for spi_flash decl)
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* }
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*/
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#ifndef DT_PLAT_C
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#define spi_flash spi_nor
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#endif
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/**
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* struct spi_nor - Structure for defining a the SPI NOR layer
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* @mtd: point to a mtd_info structure
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* @lock: the lock for the read/write/erase/lock/unlock operations
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* @dev: point to a spi device, or a spi nor controller device.
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* @info: spi-nor part JDEC MFR id and other info
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* @manufacturer_sfdp: manufacturer specific SFDP table
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* @page_size: the page size of the SPI NOR
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* @addr_width: number of address bytes
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* @erase_opcode: the opcode for erasing a sector
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* @read_opcode: the read opcode
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* @read_dummy: the dummy needed by the read operation
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* @program_opcode: the program opcode
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* @bank_read_cmd: Bank read cmd
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* @bank_write_cmd: Bank write cmd
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* @bank_curr: Current flash bank
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* @sst_write_second: used by the SST write operation
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* @flags: flag options for the current SPI-NOR (SNOR_F_*)
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* @read_proto: the SPI protocol for read operations
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* @write_proto: the SPI protocol for write operations
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* @reg_proto the SPI protocol for read_reg/write_reg/erase operations
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* @cmd_buf: used by the write_reg
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* @prepare: [OPTIONAL] do some preparations for the
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* read/write/erase/lock/unlock operations
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* @unprepare: [OPTIONAL] do some post work after the
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* read/write/erase/lock/unlock operations
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* @read_reg: [DRIVER-SPECIFIC] read out the register
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* @write_reg: [DRIVER-SPECIFIC] write data to the register
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* @read: [DRIVER-SPECIFIC] read data from the SPI NOR
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* @write: [DRIVER-SPECIFIC] write data to the SPI NOR
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* @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
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* at the offset @offs; if not provided by the driver,
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* spi-nor will send the erase opcode via write_reg()
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* @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
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* @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
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* @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
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* @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
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* completely locked
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* @priv: the private data
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*/
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struct spi_nor {
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struct mtd_info mtd;
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struct udevice *dev;
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struct spi_slave *spi;
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const struct flash_info *info;
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u8 *manufacturer_sfdp;
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u32 page_size;
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u8 addr_width;
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u8 erase_opcode;
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u8 read_opcode;
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u8 read_dummy;
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u8 program_opcode;
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#ifdef CONFIG_SPI_FLASH_BAR
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u8 bank_read_cmd;
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u8 bank_write_cmd;
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u8 bank_curr;
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#endif
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enum spi_nor_protocol read_proto;
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enum spi_nor_protocol write_proto;
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enum spi_nor_protocol reg_proto;
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bool sst_write_second;
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u32 flags;
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u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
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int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
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int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
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ssize_t (*read)(struct spi_nor *nor, loff_t from,
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size_t len, u_char *read_buf);
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ssize_t (*write)(struct spi_nor *nor, loff_t to,
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size_t len, const u_char *write_buf);
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int (*erase)(struct spi_nor *nor, loff_t offs);
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int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
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int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
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int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
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int (*quad_enable)(struct spi_nor *nor);
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void *priv;
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/* Compatibility for spi_flash, remove once sf layer is merged with mtd */
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const char *name;
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u32 size;
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u32 sector_size;
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u32 erase_size;
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};
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#ifndef __UBOOT__
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static inline void spi_nor_set_flash_node(struct spi_nor *nor,
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const struct device_node *np)
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{
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mtd_set_of_node(&nor->mtd, np);
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}
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static inline const struct
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device_node *spi_nor_get_flash_node(struct spi_nor *nor)
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{
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return mtd_get_of_node(&nor->mtd);
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}
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#endif /* __UBOOT__ */
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/**
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* struct spi_nor_hwcaps - Structure for describing the hardware capabilies
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* supported by the SPI controller (bus master).
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* @mask: the bitmask listing all the supported hw capabilies
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*/
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struct spi_nor_hwcaps {
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u32 mask;
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};
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/*
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*(Fast) Read capabilities.
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* MUST be ordered by priority: the higher bit position, the higher priority.
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* As a matter of performances, it is relevant to use Octo SPI protocols first,
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* then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
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* (Slow) Read.
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*/
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#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
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#define SNOR_HWCAPS_READ BIT(0)
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#define SNOR_HWCAPS_READ_FAST BIT(1)
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#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
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#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
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#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
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#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
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#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
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#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
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#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
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#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
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#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
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#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
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#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
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#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
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#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
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#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
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#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
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#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
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/*
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* Page Program capabilities.
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* MUST be ordered by priority: the higher bit position, the higher priority.
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* Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
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* legacy SPI 1-1-1 protocol.
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* Note that Dual Page Programs are not supported because there is no existing
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* JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
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* implements such commands.
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*/
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#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
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#define SNOR_HWCAPS_PP BIT(16)
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#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
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#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
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#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
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#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
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#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
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#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
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#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
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#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
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|
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/**
|
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* spi_nor_scan() - scan the SPI NOR
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* @nor: the spi_nor structure
|
|
*
|
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* The drivers can use this function to scan the SPI NOR.
|
|
* In the scanning, it will try to get all the necessary information to
|
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* fill the mtd_info{} and the spi_nor{}.
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*
|
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* Return: 0 for success, others for failure.
|
|
*/
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int spi_nor_scan(struct spi_nor *nor);
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|
|
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#endif
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