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14376b8e6c
The omap24xx I2C driver uses its own CONFIG namespace for common I2C variables. Rather than convert more of them to Kconfig, rename these to the common I2C ones and remove the entirely unused functionality. As part of this, we make the am335x_shc platforms consistent with their intended speed values. Signed-off-by: Tom Rini <trini@konsulko.com>
167 lines
3.4 KiB
C
167 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Compulab, Ltd.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <net.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/emif.h>
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#include <linux/delay.h>
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#include <power/pmic.h>
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#include <power/tps65218.h>
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#include "board.h"
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#include <usb.h>
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#include <asm/omap_common.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* setup board specific PMIC */
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int power_init_board(void)
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{
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struct pmic *p;
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uchar tps_status = 0;
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power_tps65218_init(I2C_PMIC);
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p = pmic_get("TPS65218_PMIC");
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if (p && !pmic_probe(p)) {
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puts("PMIC: TPS65218\n");
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/* We don't care if fseal is locked, but we do need it set */
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tps65218_lock_fseal();
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tps65218_reg_read(TPS65218_STATUS, &tps_status);
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if (!(tps_status & TPS65218_FSEAL))
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printf("WARNING: RTC not backed by battery!\n");
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}
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gpmc_init();
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set_i2c_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_probe(TPS65218_CHIP_PM);
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return 0;
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}
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int board_usb_init(int index, enum usb_init_type init)
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{
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enable_usb_clocks(index);
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return 0;
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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disable_usb_clocks(index);
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return 0;
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}
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#ifdef CONFIG_DRIVER_TI_CPSW
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static void cpsw_control(int enabled)
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{
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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.phy_if = PHY_INTERFACE_MODE_RGMII,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_addr = 1,
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.phy_if = PHY_INTERFACE_MODE_RGMII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 2,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#define GPIO_PHY1_RST 170
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#define GPIO_PHY2_RST 168
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int board_phy_config(struct phy_device *phydev)
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{
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unsigned short val;
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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if (phydev->drv->config)
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return phydev->drv->config(phydev);
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return 0;
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}
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static void board_phy_init(void)
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{
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set_mdio_pin_mux();
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writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
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writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
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writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
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/* For revision A */
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writel(0x2000009, 0x44df2e6c);
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writel(0x38a, 0x44df2e70);
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mdelay(10);
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gpio_request(GPIO_PHY1_RST, "phy1_rst");
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gpio_request(GPIO_PHY2_RST, "phy2_rst");
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gpio_direction_output(GPIO_PHY1_RST, 0);
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gpio_direction_output(GPIO_PHY2_RST, 0);
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mdelay(2);
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gpio_set_value(GPIO_PHY1_RST, 1);
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gpio_set_value(GPIO_PHY2_RST, 1);
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mdelay(2);
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}
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int board_eth_init(struct bd_info *bis)
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{
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int rv;
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set_rgmii_pin_mux();
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writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
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board_phy_init();
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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return rv;
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}
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#endif
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