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https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
132 lines
3.4 KiB
C
132 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* keystone2: common pll clock definitions
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#ifndef _CLOCK_DEFS_H_
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#define _CLOCK_DEFS_H_
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#include <asm/arch/hardware.h>
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/* PLL Control Registers */
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struct pllctl_regs {
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u32 ctl; /* 00 */
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u32 ocsel; /* 04 */
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u32 secctl; /* 08 */
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u32 resv0;
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u32 mult; /* 10 */
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u32 prediv; /* 14 */
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u32 div1; /* 18 */
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u32 div2; /* 1c */
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u32 div3; /* 20 */
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u32 oscdiv1; /* 24 */
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u32 resv1; /* 28 */
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u32 bpdiv; /* 2c */
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u32 wakeup; /* 30 */
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u32 resv2;
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u32 cmd; /* 38 */
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u32 stat; /* 3c */
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u32 alnctl; /* 40 */
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u32 dchange; /* 44 */
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u32 cken; /* 48 */
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u32 ckstat; /* 4c */
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u32 systat; /* 50 */
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u32 ckctl; /* 54 */
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u32 resv3[2];
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u32 div4; /* 60 */
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u32 div5; /* 64 */
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u32 div6; /* 68 */
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u32 div7; /* 6c */
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u32 div8; /* 70 */
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u32 div9; /* 74 */
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u32 div10; /* 78 */
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u32 div11; /* 7c */
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u32 div12; /* 80 */
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};
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static struct pllctl_regs *pllctl_regs[] = {
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(struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
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};
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#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
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#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
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#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
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#define pllctl_reg_rmw(pll, reg, mask, val) \
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pllctl_reg_write(pll, reg, \
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(pllctl_reg_read(pll, reg) & ~(mask)) | val)
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#define pllctl_reg_setbits(pll, reg, mask) \
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pllctl_reg_rmw(pll, reg, 0, mask)
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#define pllctl_reg_clrbits(pll, reg, mask) \
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pllctl_reg_rmw(pll, reg, mask, 0)
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#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
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/* PLLCTL Bits */
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#define PLLCTL_PLLENSRC_SHIF 5
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#define PLLCTL_PLLENSRC_MASK BIT(5)
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#define PLLCTL_PLLRST_SHIFT 3
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#define PLLCTL_PLLRST_MASK BIT(3)
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#define PLLCTL_PLLPWRDN_SHIFT 1
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#define PLLCTL_PLLPWRDN_MASK BIT(1)
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#define PLLCTL_PLLEN_SHIFT 0
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#define PLLCTL_PLLEN_MASK BIT(0)
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/* SECCTL Bits */
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#define SECCTL_BYPASS_SHIFT 23
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#define SECCTL_BYPASS_MASK BIT(23)
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#define SECCTL_OP_DIV_SHIFT 19
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#define SECCTL_OP_DIV_MASK (0xf << 19)
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/* PLLM Bits */
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#define PLLM_MULT_LO_SHIFT 0
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#define PLLM_MULT_LO_MASK 0x3f
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#define PLLM_MULT_LO_BITS 6
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/* PLLDIVn Bits */
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#define PLLDIV_ENABLE_SHIFT 15
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#define PLLDIV_ENABLE_MASK BIT(15)
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#define PLLDIV_RATIO_SHIFT 0x0
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#define PLLDIV_RATIO_MASK 0xff
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#define PLLDIV_MAX 16
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/* PLLCMD Bits */
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#define PLLCMD_GOSET_SHIFT 0
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#define PLLCMD_GOSET_MASK BIT(0)
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/* PLLSTAT Bits */
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#define PLLSTAT_GOSTAT_SHIFT 0
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#define PLLSTAT_GOSTAT_MASK BIT(0)
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/* Device Config PLLCTL0 */
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#define CFG_PLLCTL0_BWADJ_SHIFT 24
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#define CFG_PLLCTL0_BWADJ_MASK (0xff << 24)
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#define CFG_PLLCTL0_BWADJ_BITS 8
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#define CFG_PLLCTL0_BYPASS_SHIFT 23
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#define CFG_PLLCTL0_BYPASS_MASK BIT(23)
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#define CFG_PLLCTL0_CLKOD_SHIFT 19
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#define CFG_PLLCTL0_CLKOD_MASK (0xf << 19)
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#define CFG_PLLCTL0_PLLM_HI_SHIFT 12
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#define CFG_PLLCTL0_PLLM_HI_MASK (0x7f << 12)
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#define CFG_PLLCTL0_PLLM_SHIFT 6
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#define CFG_PLLCTL0_PLLM_MASK (0x1fff << 6)
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#define CFG_PLLCTL0_PLLD_SHIFT 0
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#define CFG_PLLCTL0_PLLD_MASK 0x3f
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/* Device Config PLLCTL1 */
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#define CFG_PLLCTL1_RST_SHIFT 14
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#define CFG_PLLCTL1_RST_MASK BIT(14)
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#define CFG_PLLCTL1_PAPLL_SHIFT 13
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#define CFG_PLLCTL1_PAPLL_MASK BIT(13)
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#define CFG_PLLCTL1_ENSAT_SHIFT 6
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#define CFG_PLLCTL1_ENSAT_MASK BIT(6)
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#define CFG_PLLCTL1_BWADJ_SHIFT 0
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#define CFG_PLLCTL1_BWADJ_MASK 0xf
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#define MISC_CTL1_ARM_PLL_EN BIT(13)
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#endif /* _CLOCK_DEFS_H_ */
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