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https://github.com/AsahiLinux/u-boot
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553f09823c
CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be some end address; to make the meaning more clear we rename it into CONFIG_SYS_INIT_RAM_SIZE No other code changes are performed in this patch, only minor editing of white space (due to the changed length) and the comments was done, where noticed. Note that the code for the PATI and cmi_mpc5xx board configurations looks seriously broken. Last known maintainers on Cc: Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Denis Peter <d.peter@mpl.ch> Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch> Acked-by: Kumar Gala <galak@kernel.crashing.org>
352 lines
11 KiB
C
352 lines
11 KiB
C
/*
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* (C) Copyright 2007
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8247 1
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#define CONFIG_MPC8272_FAMILY 1
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#define CONFIG_MGCOGE 1
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#define CONFIG_HOSTNAME mgcoge
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#define CONFIG_SYS_TEXT_BASE 0xFE000000
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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/* include common defines/options for all Keymile boards */
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#include "keymile-common.h"
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/*
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*/
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#define CONFIG_CONS_ON_SMC /* Console is on SMC */
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#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
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#undef CONFIG_CONS_NONE /* It's not on external UART */
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#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
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#define CONFIG_SYS_SMC_RXBUFLEN 128
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#define CONFIG_SYS_MAXIDLE 10
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/*
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* Select ethernet configuration
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*
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* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
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* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
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* SCC, 1-3 for FCC)
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*
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* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
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* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
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* must be unset.
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*/
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#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
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#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
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#undef CONFIG_ETHER_NONE /* No external Ethernet */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_ETHER_INDEX 4
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#define CONFIG_HAS_ETH0
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#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
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# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
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#ifndef CONFIG_8260_CLKIN
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#define CONFIG_8260_CLKIN 66000000 /* in Hz */
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#endif
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#define BOOTFLASH_START FE000000
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#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
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#define MTDIDS_DEFAULT "nor0=boot,nor1=app"
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#define MTDPARTS_DEFAULT \
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"mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \
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"app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)"
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#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
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#define CONFIG_KM_DEF_ENV "km-common=empty\0"
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#endif
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/*
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* Default environment settings
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_KM_DEF_ENV \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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"addcon=setenv bootargs ${bootargs} " \
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"console=ttyCPM0,${baudrate}\0" \
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"mtdids=nor0=boot,nor1=app \0" \
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"partition=nor1,5 \0" \
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"new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" \
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"EEprom_ivm=pca9544a:70:4 \0" \
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"mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
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"unlock=yes\0" \
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""
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFE000000
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#define CONFIG_SYS_FLASH_SIZE 32
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_BASE_1 0x50000000
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#define CONFIG_SYS_FLASH_SIZE_1 32
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#define CONFIG_SYS_FLASH_BASE_2 0x52000000
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#define CONFIG_SYS_FLASH_SIZE_2 32
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_FLASH_BASE_1, \
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CONFIG_SYS_FLASH_BASE_2 }
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384KB for Monitor */
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#define CONFIG_ENV_IS_IN_FLASH
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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#define CONFIG_ENV_BUFFER_PRINT 1
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
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#define I2C_ACTIVE (iop->pdir |= 0x00010000)
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#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
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#define I2C_READ ((iop->pdat & 0x00010000) != 0)
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#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
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else iop->pdat &= ~0x00010000
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#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
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else iop->pdat &= ~0x00020000
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_LOW_TEMP -30
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_IMMR 0xF0000000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* Hard reset configuration word */
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#define CONFIG_SYS_HRCW_MASTER 0x0604b211
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/* No slaves */
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#define CONFIG_SYS_HRCW_SLAVE1 0
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#define CONFIG_SYS_HRCW_SLAVE2 0
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#define CONFIG_SYS_HRCW_SLAVE3 0
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#define CONFIG_SYS_HRCW_SLAVE4 0
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#define CONFIG_SYS_HRCW_SLAVE5 0
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#define CONFIG_SYS_HRCW_SLAVE6 0
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#define CONFIG_SYS_HRCW_SLAVE7 0
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CONFIG_SYS_HID0_INIT 0
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#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
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#define CONFIG_SYS_HID2 0
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#define CONFIG_SYS_SIUMCR 0x4020c200
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#define CONFIG_SYS_SYPCR 0xFFFFFFC3
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#define CONFIG_SYS_BCR 0x10000000
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#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CONFIG_SYS_RMR 0
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RCCR 0
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/*
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSz Device
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* ---- --- ------- ------ ------
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* 0 60x GPCM 8 bit FLASH
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* 1 60x SDRAM 32 bit SDRAM
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* 3 60x GPCM 8 bit GPIO/PIGGY
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* 5 60x GPCM 16 bit CFG-Flash
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*
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*/
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/* Bank 0 - FLASH
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*/
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV2 |\
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ORxG_SCY_5_CLK |\
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ORxG_TRLX )
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/* Bank 1 - 60x bus SDRAM
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*/
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#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
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#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
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#define CONFIG_SYS_MPTPR 0x1800
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/*-----------------------------------------------------------------------------
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* Address for Mode Register Set (MRS) command
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*-----------------------------------------------------------------------------
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*/
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#define CONFIG_SYS_MRS_OFFS 0x00000110
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#define CONFIG_SYS_PSRT 0x0e
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#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
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/* SDRAM initialization values
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*/
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#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
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ORxS_BPD_8 |\
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ORxS_ROWST_PBI0_A7 |\
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ORxS_NUMR_13)
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#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
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PSDMR_BSMA_A14_A16 |\
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PSDMR_SDA10_PBI0_A9 |\
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PSDMR_RFRC_5_CLK |\
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PSDMR_PRETOACT_2W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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/* GPIO/PIGGY on CS3 initialization values
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*/
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#define CONFIG_SYS_PIGGY_BASE 0x30000000
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#define CONFIG_SYS_PIGGY_SIZE 128
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#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
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BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
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ORxG_CSNT | ORxG_ACS_DIV2 |\
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ORxG_SCY_3_CLK | ORxG_TRLX )
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/* Board FPGA on CS4 initialization values
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*/
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#define CONFIG_SYS_FPGA_BASE 0x40000000
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#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
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#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
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BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
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#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
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ORxG_CSNT | ORxG_ACS_DIV2 |\
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ORxG_SCY_3_CLK | ORxG_TRLX )
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/* CFG-Flash on CS5 initialization values
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*/
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#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
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BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
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#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
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CONFIG_SYS_FLASH_SIZE_2) |\
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ORxG_CSNT | ORxG_ACS_DIV2 |\
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ORxG_SCY_5_CLK | ORxG_TRLX )
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#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
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/* pass open firmware flat tree */
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#define CONFIG_FIT 1
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
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#endif /* __CONFIG_H */
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