mirror of
https://github.com/AsahiLinux/u-boot
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280 lines
8 KiB
C
280 lines
8 KiB
C
/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Manikandan Pillai <mani.pillai@ti.com>
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*
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* Initial Code from:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <command.h>
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/*
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* Only One NAND allowed on board at a time.
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* The GPMC CS Base for the same
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*/
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unsigned int boot_flash_base;
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unsigned int boot_flash_off;
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unsigned int boot_flash_sec;
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unsigned int boot_flash_type;
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volatile unsigned int boot_flash_env_addr;
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struct gpmc *gpmc_cfg;
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#if defined(CONFIG_CMD_NAND)
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static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
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M_NAND_GPMC_CONFIG1,
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M_NAND_GPMC_CONFIG2,
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M_NAND_GPMC_CONFIG3,
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M_NAND_GPMC_CONFIG4,
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M_NAND_GPMC_CONFIG5,
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M_NAND_GPMC_CONFIG6, 0
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};
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#if defined(CONFIG_ENV_IS_IN_NAND)
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#define GPMC_CS 0
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#else
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#define GPMC_CS 1
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#endif
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#endif
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#if defined(CONFIG_CMD_ONENAND)
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static const u32 gpmc_onenand[GPMC_MAX_REG] = {
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ONENAND_GPMC_CONFIG1,
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ONENAND_GPMC_CONFIG2,
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ONENAND_GPMC_CONFIG3,
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ONENAND_GPMC_CONFIG4,
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ONENAND_GPMC_CONFIG5,
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ONENAND_GPMC_CONFIG6, 0
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};
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#if defined(CONFIG_ENV_IS_IN_ONENAND)
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#define GPMC_CS 0
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#else
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#define GPMC_CS 1
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#endif
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#endif
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static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
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/**************************************************************************
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* make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
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* command line mem=xyz use all memory with out discontinuous support
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* compiled in. Could do it at the ATAG, but there really is two banks...
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* Called as part of 2nd phase DDR init.
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**************************************************************************/
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void make_cs1_contiguous(void)
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{
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u32 size, a_add_low, a_add_high;
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size = get_sdr_cs_size(CS0);
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size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
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a_add_high = (size & 3) << 8; /* set up low field */
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a_add_low = (size & 0x3C) >> 2; /* set up high field */
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writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
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}
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/********************************************************
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* mem_ok() - test used to see if timings are correct
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* for a part. Helps in guessing which part
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* we are currently using.
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*******************************************************/
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u32 mem_ok(u32 cs)
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{
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u32 val1, val2, addr;
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u32 pattern = 0x12345678;
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addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
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writel(0x0, addr + 0x400); /* clear pos A */
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writel(pattern, addr); /* pattern to pos B */
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writel(0x0, addr + 4); /* remove pattern off the bus */
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val1 = readl(addr + 0x400); /* get pos A value */
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val2 = readl(addr); /* get val2 */
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if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
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return 0;
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else
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return 1;
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}
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/********************************************************
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* sdrc_init() - init the sdrc chip selects CS0 and CS1
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* - early init routines, called from flash or
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* SRAM.
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*******************************************************/
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void sdrc_init(void)
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{
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/* only init up first bank here */
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do_sdrc_init(CS0, EARLY_INIT);
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}
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/*************************************************************************
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* do_sdrc_init(): initialize the SDRAM for use.
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* -code sets up SDRAM basic SDRC timings for CS0
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* -optimal settings can be placed here, or redone after i2c
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* inspection of board info
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*
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* - code called once in C-Stack only context for CS0 and a possible 2nd
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* time depending on memory configuration from stack+global context
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**************************************************************************/
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void do_sdrc_init(u32 cs, u32 early)
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{
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struct sdrc_actim *sdrc_actim_base;
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if(cs)
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sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
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else
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sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
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if (early) {
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/* reset sdrc controller */
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writel(SOFTRESET, &sdrc_base->sysconfig);
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wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
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12000000);
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writel(0, &sdrc_base->sysconfig);
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/* setup sdrc to ball mux */
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writel(SDRC_SHARING, &sdrc_base->sharing);
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/* Disable Power Down of CKE cuz of 1 CKE on combo part */
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writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
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writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
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sdelay(0x20000);
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}
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writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
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RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
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DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
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writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
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writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
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writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
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writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
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writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
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writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
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writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
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/*
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* CAS latency 3, Write Burst = Read Burst, Serial Mode,
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* Burst length = 4
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*/
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writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
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if (!mem_ok(cs))
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writel(0, &sdrc_base->cs[cs].mcfg);
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}
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
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u32 size)
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{
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writel(0, &cs->config7);
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sdelay(1000);
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/* Delay for settling */
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writel(gpmc_config[0], &cs->config1);
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writel(gpmc_config[1], &cs->config2);
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writel(gpmc_config[2], &cs->config3);
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writel(gpmc_config[3], &cs->config4);
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writel(gpmc_config[4], &cs->config5);
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writel(gpmc_config[5], &cs->config6);
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/* Enable the config */
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writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
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(1 << 6)), &cs->config7);
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sdelay(2000);
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}
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* Init GPMC for x16, MuxMode (SDRAM in x32).
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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/* putting a blanket check on GPMC based on ZeBu for now */
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gpmc_cfg = (struct gpmc *)GPMC_BASE;
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#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
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const u32 *gpmc_config = NULL;
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u32 base = 0;
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u32 size = 0;
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#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND)
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u32 f_off = CONFIG_SYS_MONITOR_LEN;
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u32 f_sec = 0;
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#endif
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#endif
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u32 config = 0;
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/* global settings */
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writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
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writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
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config = readl(&gpmc_cfg->config);
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config &= (~0xf00);
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writel(config, &gpmc_cfg->config);
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/*
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* Disable the GPMC0 config set by ROM code
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* It conflicts with our MPDB (both at 0x08000000)
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*/
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writel(0, &gpmc_cfg->cs[0].config7);
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sdelay(1000);
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#if defined(CONFIG_CMD_NAND) /* CS 0 */
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gpmc_config = gpmc_m_nand;
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base = PISMO1_NAND_BASE;
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size = PISMO1_NAND_SIZE;
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enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
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#if defined(CONFIG_ENV_IS_IN_NAND)
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f_off = SMNAND_ENV_OFFSET;
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f_sec = (128 << 10); /* 128 KiB */
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/* env setup */
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boot_flash_base = base;
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boot_flash_off = f_off;
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boot_flash_sec = f_sec;
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boot_flash_env_addr = f_off;
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#endif
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#endif
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#if defined(CONFIG_CMD_ONENAND)
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gpmc_config = gpmc_onenand;
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base = PISMO1_ONEN_BASE;
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size = PISMO1_ONEN_SIZE;
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enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
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#if defined(CONFIG_ENV_IS_IN_ONENAND)
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f_off = ONENAND_ENV_OFFSET;
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f_sec = (128 << 10); /* 128 KiB */
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/* env setup */
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boot_flash_base = base;
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boot_flash_off = f_off;
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boot_flash_sec = f_sec;
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boot_flash_env_addr = f_off;
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#endif
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#endif
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}
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