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a8483505e8
With patch 49b23e035d (pci: mvebu: Increase size of PCIe default mapping)
the mapping size for each PCI(e) controller was increased from 32MiB to
128MiB. This leads to problems on boards with multiple PCIe slots / ports
which are unable to map all PCIe ports, e.g. the Armada-XP theadorable:
DRAM: 2 GiB (667 MHz, 64-bit, ECC not enabled)
SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB
Cannot add window '4:f8', conflicts with another window
PCIe unable to add mbus window for mem at f0000000+08000000
Model: Marvell Armada XP theadorable
This patch moves the base address for the PCI(e) memory spaces from
0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now).
This gives move room and flexibility for PCI(e) mappings.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: VlaoMao <vlaomao@gmail.com>
Tested-by: VlaoMao <vlaomao at gmail.com>
181 lines
3.5 KiB
C
181 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#ifndef _MVEBU_CPU_H
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#define _MVEBU_CPU_H
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#include <asm/system.h>
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#ifndef __ASSEMBLY__
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#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
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#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
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enum memory_bank {
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BANK0,
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BANK1,
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BANK2,
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BANK3
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};
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enum cpu_winen {
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CPU_WIN_DISABLE,
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CPU_WIN_ENABLE
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};
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enum cpu_target {
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CPU_TARGET_DRAM = 0x0,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
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CPU_TARGET_ETH23 = 0x3,
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CPU_TARGET_PCIE02 = 0x4,
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CPU_TARGET_ETH01 = 0x7,
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CPU_TARGET_PCIE13 = 0x8,
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CPU_TARGET_SASRAM = 0x9,
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CPU_TARGET_SATA01 = 0xa, /* A38X */
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CPU_TARGET_NAND = 0xd,
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CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
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};
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enum cpu_attrib {
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CPU_ATTR_SASRAM = 0x01,
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CPU_ATTR_DRAM_CS0 = 0x0e,
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CPU_ATTR_DRAM_CS1 = 0x0d,
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CPU_ATTR_DRAM_CS2 = 0x0b,
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CPU_ATTR_DRAM_CS3 = 0x07,
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CPU_ATTR_NANDFLASH = 0x2f,
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CPU_ATTR_SPIFLASH = 0x1e,
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CPU_ATTR_SPI0_CS0 = 0x1e,
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CPU_ATTR_SPI0_CS1 = 0x5e,
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CPU_ATTR_SPI1_CS2 = 0x9a,
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CPU_ATTR_BOOTROM = 0x1d,
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CPU_ATTR_PCIE_IO = 0xe0,
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CPU_ATTR_PCIE_MEM = 0xe8,
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CPU_ATTR_DEV_CS0 = 0x3e,
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CPU_ATTR_DEV_CS1 = 0x3d,
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CPU_ATTR_DEV_CS2 = 0x3b,
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CPU_ATTR_DEV_CS3 = 0x37,
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};
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enum {
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MVEBU_SOC_AXP,
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MVEBU_SOC_A375,
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MVEBU_SOC_A38X,
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MVEBU_SOC_MSYS,
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MVEBU_SOC_UNKNOWN,
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};
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#define MVEBU_SDRAM_SIZE_MAX 0xc0000000
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/*
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* Default Device Address MAP BAR values
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*/
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#define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX
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#define MBUS_PCI_MEM_SIZE (128 << 20)
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#define MBUS_PCI_IO_BASE 0xF1100000
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#define MBUS_PCI_IO_SIZE (64 << 10)
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#define MBUS_SPI_BASE 0xF4000000
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#define MBUS_SPI_SIZE (8 << 20)
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#define MBUS_BOOTROM_BASE 0xF8000000
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#define MBUS_BOOTROM_SIZE (8 << 20)
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struct mbus_win {
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u32 base;
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u32 size;
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u8 target;
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u8 attr;
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};
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/*
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* System registers
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* Ref: Datasheet sec:A.28
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*/
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struct mvebu_system_registers {
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#if defined(CONFIG_ARMADA_375)
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u8 pad1[0x54];
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#else
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u8 pad1[0x60];
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#endif
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u32 rstoutn_mask; /* 0x60 */
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u32 sys_soft_rst; /* 0x64 */
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};
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/*
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* GPIO Registers
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* Ref: Datasheet sec:A.19
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*/
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struct kwgpio_registers {
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u32 dout;
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u32 oe;
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u32 blink_en;
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u32 din_pol;
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u32 din;
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u32 irq_cause;
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u32 irq_mask;
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u32 irq_level;
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};
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struct sar_freq_modes {
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u8 val;
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u8 ffc; /* Fabric Frequency Configuration */
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u32 p_clk;
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u32 nb_clk;
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u32 d_clk;
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};
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/* Needed for dynamic (board-specific) mbus configuration */
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extern struct mvebu_mbus_state mbus_state;
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/*
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* functions
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*/
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unsigned int mvebu_sdram_bar(enum memory_bank bank);
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unsigned int mvebu_sdram_bs(enum memory_bank bank);
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void mvebu_sdram_size_adjust(enum memory_bank bank);
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int mvebu_mbus_probe(struct mbus_win windows[], int count);
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int mvebu_soc_family(void);
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u32 mvebu_get_nand_clock(void);
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void return_to_bootrom(void);
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int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
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void get_sar_freq(struct sar_freq_modes *sar_freq);
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/*
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* Highspeed SERDES PHY config init, ported from bin_hdr
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* to mainline U-Boot
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*/
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int serdes_phy_config(void);
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/*
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* DDR3 init / training code ported from Marvell bin_hdr. Now
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* available in mainline U-Boot in:
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* drivers/ddr/marvell
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*/
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int ddr3_init(void);
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struct mvebu_lcd_info {
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u32 fb_base;
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int x_res;
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int y_res;
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int x_fp; /* frontporch */
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int y_fp;
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int x_bp; /* backporch */
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int y_bp;
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};
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int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
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/*
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* get_ref_clk
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*
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* return: reference clock in MHz (25 or 40)
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*/
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u32 get_ref_clk(void);
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#endif /* __ASSEMBLY__ */
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#endif /* _MVEBU_CPU_H */
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