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40109f4d7e
On K3 devices there are 2 conditions where R5F can deadlock: 1.When software is performing series of store operations to cacheable write back/write allocate memory region and later on software execute barrier operation (DSB or DMB). R5F may hang at the barrier instruction. 2.When software is performing a mix of load and store operations within a tight loop and store operations are all writing to cacheable write back/write allocates memory regions, R5F may hang at one of the load instruction. To avoid the above two conditions disable linefill optimization inside Cortex R5F which will make R5F to only issue up to 2 cache line fills at any point of time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
19 lines
408 B
C
19 lines
408 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: Architecture common definitions
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <asm/armv7_mpu.h>
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#define AM654 2
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#define J721E 4
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#define REV_PG1_0 0
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#define REV_PG2_0 1
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void setup_k3_mpu_regions(void);
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int early_console_init(void);
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void disable_linefill_optimization(void);
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