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https://github.com/AsahiLinux/u-boot
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c1466c55de
Add compatible values to Ethernet PHY subnodes representing SMSC LAN8710A PHYs on RZ/A1 and R-Mobile A1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Ported from Linux kernel commit 1c65ef1c71e473c00f2a7a1b9c140f0b4862f282 . Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/247dc2074dae149af07b6d014985ad30eb362eda.1631174218.git.geert+renesas@glider.be --- Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@amd.com> Cc: Nishanth Menon <nm@ti.com> Cc: Ramon Fried <rfried.dev@gmail.com>
136 lines
2.8 KiB
Text
136 lines
2.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the GR-Peach board
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*
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* Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
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* Copyright (C) 2016 Renesas Electronics
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*/
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/dts-v1/;
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#include "r7s72100.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
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/ {
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model = "GR-Peach";
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compatible = "renesas,gr-peach", "renesas,r7s72100";
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aliases {
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serial0 = &scif2;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
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stdout-path = "serial0:115200n8";
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};
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memory@20000000 {
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device_type = "memory";
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reg = <0x20000000 0x00a00000>;
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};
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lbsc {
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#address-cells = <1>;
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#size-cells = <1>;
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};
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flash@18000000 {
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compatible = "mtd-rom";
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probe-type = "map_rom";
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reg = <0x18000000 0x00800000>;
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bank-width = <4>;
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device-width = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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rootfs@600000 {
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label = "rootfs";
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reg = <0x00600000 0x00200000>;
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};
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};
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leds {
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status = "okay";
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compatible = "gpio-leds";
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led1 {
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gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&pinctrl {
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scif2_pins: serial2 {
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/* P6_2 as RxD2; P6_3 as TxD2 */
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pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
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};
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ether_pins: ether {
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/* Ethernet on Ports 1,3,5,10 */
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pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
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<RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
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<RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
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<RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
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<RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
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<RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
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<RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
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<RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
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<RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
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<RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
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<RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
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<RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
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<RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
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<RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
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<RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
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<RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
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<RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
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<RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
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};
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};
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&extal_clk {
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clock-frequency = <13333000>;
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};
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&usb_x1_clk {
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clock-frequency = <48000000>;
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};
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&mtu2 {
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status = "okay";
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};
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&ostm0 {
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status = "okay";
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};
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&ostm1 {
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status = "okay";
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};
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&scif2 {
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pinctrl-names = "default";
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pinctrl-0 = <&scif2_pins>;
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status = "okay";
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};
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ðer {
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pinctrl-names = "default";
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pinctrl-0 = <ðer_pins>;
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status = "okay";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0007.c0f0",
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
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reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
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reset-delay-us = <5>;
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};
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};
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