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05c7606ac9
Adds support for NAND controllers found on OcteonTX or OcteonTX2 SoC platforms. Also includes driver to support Hardware ECC using BCH HW engine found on these platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
131 lines
3.7 KiB
C
131 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#ifndef __OCTEONTX_BCH_H__
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#define __OCTEONTX_BCH_H__
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#include "octeontx_bch_regs.h"
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/* flags to indicate the features supported */
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#define BCH_FLAG_SRIOV_ENABLED BIT(1)
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/*
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* BCH Registers map for 81xx
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*/
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/* PF registers */
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#define BCH_CTL 0x0ull
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#define BCH_ERR_CFG 0x10ull
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#define BCH_BIST_RESULT 0x80ull
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#define BCH_ERR_INT 0x88ull
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#define BCH_ERR_INT_W1S 0x90ull
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#define BCH_ERR_INT_ENA_W1C 0xA0ull
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#define BCH_ERR_INT_ENA_W1S 0xA8ull
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/* VF registers */
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#define BCH_VQX_CTL(z) 0x0ull
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#define BCH_VQX_CMD_BUF(z) 0x8ull
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#define BCH_VQX_CMD_PTR(z) 0x20ull
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#define BCH_VQX_DOORBELL(z) 0x800ull
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#define BCHPF_DRIVER_NAME "octeontx-bchpf"
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#define BCHVF_DRIVER_NAME "octeontx-bchvf"
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struct bch_device {
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struct list_head list;
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u8 max_vfs;
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u8 vfs_enabled;
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u8 vfs_in_use;
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u32 flags;
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void __iomem *reg_base;
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struct udevice *dev;
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};
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struct bch_vf {
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u16 flags;
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u8 vfid;
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u8 node;
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u8 priority;
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struct udevice *dev;
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void __iomem *reg_base;
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};
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struct buf_ptr {
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u8 *vptr;
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dma_addr_t dma_addr;
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u16 size;
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};
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void *octeontx_bch_getv(void);
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void octeontx_bch_putv(void *token);
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void *octeontx_bch_getp(void);
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void octeontx_bch_putp(void *token);
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int octeontx_bch_wait(struct bch_vf *vf, union bch_resp *resp,
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dma_addr_t handle);
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/**
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* Given a data block calculate the ecc data and fill in the response
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*
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* @param[in] block 8-byte aligned pointer to data block to calculate ECC
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* @param block_size Size of block in bytes, must be a multiple of two.
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* @param bch_level Number of errors that must be corrected. The number of
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* parity bytes is equal to ((15 * bch_level) + 7) / 8.
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* Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64.
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* @param[out] ecc 8-byte aligned pointer to where ecc data should go
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* @param[in] resp pointer to where responses will be written.
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*
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* @return Zero on success, negative on failure.
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*/
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int octeontx_bch_encode(struct bch_vf *vf, dma_addr_t block, u16 block_size,
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u8 bch_level, dma_addr_t ecc, dma_addr_t resp);
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/**
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* Given a data block and ecc data correct the data block
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*
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* @param[in] block_ecc_in 8-byte aligned pointer to data block with ECC
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* data concatenated to the end to correct
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* @param block_size Size of block in bytes, must be a multiple of
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* two.
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* @param bch_level Number of errors that must be corrected. The
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* number of parity bytes is equal to
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* ((15 * bch_level) + 7) / 8.
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* Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64.
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* @param[out] block_out 8-byte aligned pointer to corrected data buffer.
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* This should not be the same as block_ecc_in.
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* @param[in] resp pointer to where responses will be written.
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*
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* @return Zero on success, negative on failure.
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*/
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int octeontx_bch_decode(struct bch_vf *vf, dma_addr_t block_ecc_in,
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u16 block_size, u8 bch_level,
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dma_addr_t block_out, dma_addr_t resp);
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/**
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* Ring the BCH doorbell telling it that new commands are
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* available.
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*
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* @param num_commands Number of new commands
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* @param vf virtual function handle
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*/
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static inline void octeontx_bch_write_doorbell(u64 num_commands,
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struct bch_vf *vf)
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{
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u64 num_words = num_commands * sizeof(union bch_cmd) / sizeof(uint64_t);
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writeq(num_words, vf->reg_base + BCH_VQX_DOORBELL(0));
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}
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/**
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* Since it's possible (and even likely) that the NAND device will be probed
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* before the BCH device has been probed, we may need to defer the probing.
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*
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* In this case, the initial probe returns success but the actual probing
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* is deferred until the BCH VF has been probed.
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*
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* @return 0 for success, otherwise error
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*/
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int octeontx_pci_nand_deferred_probe(void);
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#endif /* __OCTEONTX_BCH_H__ */
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