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95d3e1d090
1. add the address mapping related properties; 2. make "ref" clock optional, and add optional clock "da_ref"; 3. add the banks layout of TPHY V1 and V2; Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
144 lines
4.3 KiB
Text
144 lines
4.3 KiB
Text
MediaTek T-PHY binding
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--------------------------
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T-phy controller supports physical layer functionality for a number of
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controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
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Required properties (controller (parent) node):
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- compatible : should be one of
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"mediatek,generic-tphy-v1"
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"mediatek,generic-tphy-v2"
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- #address-cells: the number of cells used to represent physical
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base addresses.
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- #size-cells: the number of cells used to represent the size of an address.
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- ranges: the address mapping relationship to the parent, defined with
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- empty value: if optional 'reg' is used.
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- non-empty value: if optional 'reg' is not used. should set
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the child's base address to 0, the physical address
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within parent's address space, and the length of
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the address map.
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Required nodes : a sub-node is required for each port the controller
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provides. Address range information including the usual
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'reg' property is used inside these nodes to describe
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the controller's topology.
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Optional properties (controller (parent) node):
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- reg : offset and length of register shared by multiple ports,
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exclude port's private register.
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- mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
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calibrate
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- mediatek,src-coef : coefficient for slew rate calibrate, depends on
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SoC process
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Required properties (port (child) node):
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- reg : address and length of the register set for the port.
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- #phy-cells : should be 1 (See second example)
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cell after port phandle is phy type from:
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- PHY_TYPE_USB2
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- PHY_TYPE_USB3
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- PHY_TYPE_PCIE
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- PHY_TYPE_SATA
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Optional properties (port (child) node):
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- clocks : a list of phandle + clock-specifier pairs, one for each
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entry in clock-names
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- clock-names : may contain
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"ref": 48M reference clock for HighSpeed (digital) phy; and 26M
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reference clock for SuperSpeed (digital) phy, sometimes is
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24M, 25M or 27M, depended on platform.
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"da_ref": the reference clock of analog phy, used if the clocks
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of analog and digital phys are separated, otherwise uses
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"ref" clock only if needed.
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Example:
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u3phy2: usb-phy@1a244000 {
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compatible = "mediatek,generic-tphy-v1";
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reg = <0x1a244000 0x0700>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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u2port1: usb-phy@1a244800 {
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reg = <0x1a244800 0x0100>;
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clocks = <&topckgen CLK_TOP_USB_PHY48M>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u3port1: usb-phy@1a244900 {
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reg = <0x1a244900 0x0700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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};
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Specifying phy control of devices
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---------------------------------
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Device nodes should specify the configuration required in their "phys"
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property, containing a phandle to the phy port node and a device type;
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phy-names for each port are optional.
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Example:
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#include <dt-bindings/phy/phy.h>
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usb30: usb@11270000 {
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...
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phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
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phy-names = "usb2-0", "usb3-0";
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...
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};
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Layout differences of banks between TPHY V1 and V2
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-------------------------------------------------------------
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IP V1:
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port offset bank
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shared 0x0000 SPLLC
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0x0100 FMREG
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u2 port0 0x0800 U2PHY_COM
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u3 port0 0x0900 U3PHYD
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0x0a00 U3PHYD_BANK2
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0x0b00 U3PHYA
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0x0c00 U3PHYA_DA
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u2 port1 0x1000 U2PHY_COM
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u3 port1 0x1100 U3PHYD
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0x1200 U3PHYD_BANK2
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0x1300 U3PHYA
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0x1400 U3PHYA_DA
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u2 port2 0x1800 U2PHY_COM
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...
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IP V2:
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port offset bank
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u2 port0 0x0000 MISC
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0x0100 FMREG
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0x0300 U2PHY_COM
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u3 port0 0x0700 SPLLC
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0x0800 CHIP
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0x0900 U3PHYD
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0x0a00 U3PHYD_BANK2
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0x0b00 U3PHYA
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0x0c00 U3PHYA_DA
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u2 port1 0x1000 MISC
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0x1100 FMREG
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0x1300 U2PHY_COM
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u3 port1 0x1700 SPLLC
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0x1800 CHIP
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0x1900 U3PHYD
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0x1a00 U3PHYD_BANK2
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0x1b00 U3PHYA
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0x1c00 U3PHYA_DA
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u2 port2 0x2000 MISC
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...
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SPLLC shared by u3 ports and FMREG shared by u2 ports on
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TPHY V1 are put back into each port; a new bank MISC for
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u2 ports and CHIP for u3 ports are added on TPHY V2.
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