mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 10:30:32 +00:00
10441ec922
This patch is enabling GPIO_DM support to have an option to use this driver together with zynq gpio driver. !DM part is kept there till Microblaze is cleanup which will be done hopefully soon. Just a note: There is no reason to initialize uc-priv->name because it is completely unused. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
610 lines
14 KiB
C
610 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2013 - 2018 Xilinx, Michal Simek
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*/
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#include <common.h>
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#include <errno.h>
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#include <malloc.h>
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#include <linux/list.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <dm.h>
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static LIST_HEAD(gpio_list);
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enum gpio_direction {
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GPIO_DIRECTION_OUT = 0,
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GPIO_DIRECTION_IN = 1,
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};
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/* Gpio simple map */
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struct gpio_regs {
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u32 gpiodata;
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u32 gpiodir;
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};
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#if !defined(CONFIG_DM_GPIO)
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#define GPIO_NAME_SIZE 10
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struct gpio_names {
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char name[GPIO_NAME_SIZE];
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};
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/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
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struct xilinx_gpio_priv {
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struct gpio_regs *regs;
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u32 gpio_min;
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u32 gpio_max;
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u32 gpiodata_store;
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char name[GPIO_NAME_SIZE];
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struct list_head list;
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struct gpio_names *gpio_name;
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};
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/* Store number of allocated gpio pins */
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static u32 xilinx_gpio_max;
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/* Get associated gpio controller */
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static struct xilinx_gpio_priv *gpio_get_controller(unsigned gpio)
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{
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struct list_head *entry;
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struct xilinx_gpio_priv *priv = NULL;
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list_for_each(entry, &gpio_list) {
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priv = list_entry(entry, struct xilinx_gpio_priv, list);
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if (gpio >= priv->gpio_min && gpio <= priv->gpio_max) {
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debug("%s: reg: %x, min-max: %d-%d\n", __func__,
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(u32)priv->regs, priv->gpio_min, priv->gpio_max);
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return priv;
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}
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}
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puts("!!!Can't get gpio controller!!!\n");
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return NULL;
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}
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/* Get gpio pin name if used/setup */
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static char *get_name(unsigned gpio)
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{
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u32 gpio_priv;
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struct xilinx_gpio_priv *priv;
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debug("%s\n", __func__);
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priv = gpio_get_controller(gpio);
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if (priv) {
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gpio_priv = gpio - priv->gpio_min;
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return *priv->gpio_name[gpio_priv].name ?
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priv->gpio_name[gpio_priv].name : "UNKNOWN";
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}
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return "UNKNOWN";
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}
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/* Get output value */
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static int gpio_get_output_value(unsigned gpio)
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{
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u32 val, gpio_priv;
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struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
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if (priv) {
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gpio_priv = gpio - priv->gpio_min;
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val = !!(priv->gpiodata_store & (1 << gpio_priv));
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debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
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(u32)priv->regs, gpio_priv, val);
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return val;
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}
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return -1;
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}
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/* Get input value */
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static int gpio_get_input_value(unsigned gpio)
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{
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u32 val, gpio_priv;
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struct gpio_regs *regs;
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struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
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if (priv) {
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regs = priv->regs;
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gpio_priv = gpio - priv->gpio_min;
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val = readl(®s->gpiodata);
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val = !!(val & (1 << gpio_priv));
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debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
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(u32)priv->regs, gpio_priv, val);
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return val;
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}
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return -1;
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}
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/* Set gpio direction */
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static int gpio_set_direction(unsigned gpio, enum gpio_direction direction)
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{
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u32 val, gpio_priv;
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struct gpio_regs *regs;
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struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
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if (priv) {
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regs = priv->regs;
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val = readl(®s->gpiodir);
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gpio_priv = gpio - priv->gpio_min;
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if (direction == GPIO_DIRECTION_OUT)
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val &= ~(1 << gpio_priv);
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else
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val |= 1 << gpio_priv;
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writel(val, ®s->gpiodir);
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debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
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(u32)priv->regs, gpio_priv, val);
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return 0;
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}
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return -1;
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}
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/* Get gpio direction */
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static int gpio_get_direction(unsigned gpio)
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{
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u32 val, gpio_priv;
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struct gpio_regs *regs;
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struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
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if (priv) {
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regs = priv->regs;
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gpio_priv = gpio - priv->gpio_min;
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val = readl(®s->gpiodir);
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val = !!(val & (1 << gpio_priv));
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debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
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(u32)priv->regs, gpio_priv, val);
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return val;
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}
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return -1;
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}
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/*
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* Get input value
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* for example gpio setup to output only can't get input value
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* which is breaking gpio toggle command
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*/
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int gpio_get_value(unsigned gpio)
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{
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u32 val;
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if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
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val = gpio_get_output_value(gpio);
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else
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val = gpio_get_input_value(gpio);
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return val;
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}
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/* Set output value */
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static int gpio_set_output_value(unsigned gpio, int value)
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{
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u32 val, gpio_priv;
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struct gpio_regs *regs;
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struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
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if (priv) {
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regs = priv->regs;
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gpio_priv = gpio - priv->gpio_min;
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val = priv->gpiodata_store;
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if (value)
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val |= 1 << gpio_priv;
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else
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val &= ~(1 << gpio_priv);
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writel(val, ®s->gpiodata);
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debug("%s: reg: %x, gpio_no: %d, output_val: %d\n", __func__,
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(u32)priv->regs, gpio_priv, val);
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priv->gpiodata_store = val;
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return 0;
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}
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return -1;
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}
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int gpio_set_value(unsigned gpio, int value)
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{
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if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
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return gpio_set_output_value(gpio, value);
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return -1;
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}
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/* Set GPIO as input */
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int gpio_direction_input(unsigned gpio)
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{
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debug("%s\n", __func__);
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return gpio_set_direction(gpio, GPIO_DIRECTION_IN);
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}
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/* Setup GPIO as output and set output value */
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int gpio_direction_output(unsigned gpio, int value)
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{
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int ret = gpio_set_direction(gpio, GPIO_DIRECTION_OUT);
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debug("%s\n", __func__);
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if (ret < 0)
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return ret;
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return gpio_set_output_value(gpio, value);
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}
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/* Show gpio status */
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void gpio_info(void)
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{
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unsigned gpio;
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struct list_head *entry;
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struct xilinx_gpio_priv *priv = NULL;
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list_for_each(entry, &gpio_list) {
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priv = list_entry(entry, struct xilinx_gpio_priv, list);
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printf("\n%s: %s/%x (%d-%d)\n", __func__, priv->name,
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(u32)priv->regs, priv->gpio_min, priv->gpio_max);
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for (gpio = priv->gpio_min; gpio <= priv->gpio_max; gpio++) {
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printf("GPIO_%d:\t%s is an ", gpio, get_name(gpio));
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if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
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printf("OUTPUT value = %d\n",
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gpio_get_output_value(gpio));
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else
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printf("INPUT value = %d\n",
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gpio_get_input_value(gpio));
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}
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}
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}
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int gpio_request(unsigned gpio, const char *label)
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{
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u32 gpio_priv;
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struct xilinx_gpio_priv *priv;
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if (gpio >= xilinx_gpio_max)
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return -EINVAL;
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priv = gpio_get_controller(gpio);
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if (priv) {
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gpio_priv = gpio - priv->gpio_min;
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if (label != NULL) {
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strncpy(priv->gpio_name[gpio_priv].name, label,
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GPIO_NAME_SIZE);
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priv->gpio_name[gpio_priv].name[GPIO_NAME_SIZE - 1] =
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'\0';
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}
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return 0;
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}
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return -1;
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}
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int gpio_free(unsigned gpio)
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{
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u32 gpio_priv;
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struct xilinx_gpio_priv *priv;
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if (gpio >= xilinx_gpio_max)
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return -EINVAL;
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priv = gpio_get_controller(gpio);
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if (priv) {
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gpio_priv = gpio - priv->gpio_min;
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priv->gpio_name[gpio_priv].name[0] = '\0';
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/* Do nothing here */
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return 0;
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}
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return -1;
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}
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int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no)
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{
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struct xilinx_gpio_priv *priv;
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priv = calloc(1, sizeof(struct xilinx_gpio_priv));
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/* Setup gpio name */
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if (name != NULL) {
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strncpy(priv->name, name, GPIO_NAME_SIZE);
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priv->name[GPIO_NAME_SIZE - 1] = '\0';
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}
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priv->regs = (struct gpio_regs *)baseaddr;
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priv->gpio_min = xilinx_gpio_max;
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xilinx_gpio_max = priv->gpio_min + gpio_no;
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priv->gpio_max = xilinx_gpio_max - 1;
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priv->gpio_name = calloc(gpio_no, sizeof(struct gpio_names));
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INIT_LIST_HEAD(&priv->list);
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list_add_tail(&priv->list, &gpio_list);
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printf("%s: Add %s (%d-%d)\n", __func__, name,
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priv->gpio_min, priv->gpio_max);
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/* Return the first gpio allocated for this device */
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return priv->gpio_min;
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}
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/* Dual channel gpio is one IP with two independent channels */
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int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0, u32 gpio_no1)
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{
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int ret;
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ret = gpio_alloc(baseaddr, name, gpio_no0);
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gpio_alloc(baseaddr + 8, strcat((char *)name, "_1"), gpio_no1);
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/* Return the first gpio allocated for this device */
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return ret;
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}
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#else
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#include <dt-bindings/gpio/gpio.h>
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#define XILINX_GPIO_MAX_BANK 2
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struct xilinx_gpio_platdata {
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struct gpio_regs *regs;
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int bank_max[XILINX_GPIO_MAX_BANK];
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int bank_input[XILINX_GPIO_MAX_BANK];
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int bank_output[XILINX_GPIO_MAX_BANK];
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};
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static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
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u32 *bank_pin_num, struct udevice *dev)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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u32 bank, max_pins;
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/* the first gpio is 0 not 1 */
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u32 pin_num = offset;
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for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
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max_pins = platdata->bank_max[bank];
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if (pin_num < max_pins) {
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debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
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bank, pin_num);
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*bank_num = bank;
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*bank_pin_num = pin_num;
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return 0;
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}
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pin_num -= max_pins;
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}
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return -EINVAL;
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}
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static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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int val, ret;
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u32 bank, pin;
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ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
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if (ret)
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return ret;
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debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x\n",
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__func__, (ulong)platdata->regs, value, offset, bank, pin);
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if (value) {
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val = readl(&platdata->regs->gpiodata + bank * 2);
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val = val | (1 << pin);
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writel(val, &platdata->regs->gpiodata + bank * 2);
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} else {
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val = readl(&platdata->regs->gpiodata + bank * 2);
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val = val & ~(1 << pin);
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writel(val, &platdata->regs->gpiodata + bank * 2);
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}
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return val;
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};
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static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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int val, ret;
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u32 bank, pin;
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ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
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if (ret)
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return ret;
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debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
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(ulong)platdata->regs, offset, bank, pin);
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val = readl(&platdata->regs->gpiodata + bank * 2);
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val = !!(val & (1 << pin));
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return val;
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};
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static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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int val, ret;
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u32 bank, pin;
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/* Check if all pins are inputs */
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if (platdata->bank_input[bank])
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return GPIOF_INPUT;
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/* Check if all pins are outputs */
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if (platdata->bank_output[bank])
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return GPIOF_OUTPUT;
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ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
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if (ret)
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return ret;
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/* FIXME test on dual */
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val = readl(&platdata->regs->gpiodir + bank * 2);
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val = !(val & (1 << pin));
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/* input is 1 in reg but GPIOF_INPUT is 0 */
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/* output is 0 in reg but GPIOF_OUTPUT is 1 */
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return val;
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}
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static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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int val, ret;
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u32 bank, pin;
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ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
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if (ret)
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return ret;
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/* can't change it if all is input by default */
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if (platdata->bank_input[bank])
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return -EINVAL;
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if (!platdata->bank_output[bank]) {
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val = readl(&platdata->regs->gpiodir + bank * 2);
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val = val & ~(1 << pin);
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writel(val, &platdata->regs->gpiodir + bank * 2);
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}
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xilinx_gpio_set_value(dev, offset, value);
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return 0;
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}
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static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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int val, ret;
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u32 bank, pin;
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ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
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if (ret)
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return ret;
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/* Already input */
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if (platdata->bank_input[bank])
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return 0;
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/* can't change it if all is output by default */
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if (platdata->bank_output[bank])
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return -EINVAL;
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val = readl(&platdata->regs->gpiodir + bank * 2);
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val = val | (1 << pin);
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writel(val, &platdata->regs->gpiodir + bank * 2);
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return 0;
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}
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static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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desc->offset = args->args[0];
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debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
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args->args_count, args->args[0], args->args[1], args->args[2]);
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/*
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* The second cell is channel offset:
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* 0 is first channel, 8 is second channel
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*
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* U-Boot driver just combine channels together that's why simply
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* add amount of pins in second channel if present.
|
|
*/
|
|
if (args->args[1]) {
|
|
if (!platdata->bank_max[1]) {
|
|
printf("%s: %s has no second channel\n",
|
|
__func__, dev->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
desc->offset += platdata->bank_max[0];
|
|
}
|
|
|
|
/* The third cell is optional */
|
|
if (args->args_count > 2)
|
|
desc->flags = (args->args[2] &
|
|
GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
|
|
|
|
debug("%s: offset %x, flags %lx\n",
|
|
__func__, desc->offset, desc->flags);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_gpio_ops xilinx_gpio_ops = {
|
|
.direction_input = xilinx_gpio_direction_input,
|
|
.direction_output = xilinx_gpio_direction_output,
|
|
.get_value = xilinx_gpio_get_value,
|
|
.set_value = xilinx_gpio_set_value,
|
|
.get_function = xilinx_gpio_get_function,
|
|
.xlate = xilinx_gpio_xlate,
|
|
};
|
|
|
|
static int xilinx_gpio_probe(struct udevice *dev)
|
|
{
|
|
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
|
|
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
|
|
|
|
uc_priv->bank_name = dev->name;
|
|
|
|
uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
|
|
int is_dual;
|
|
|
|
platdata->regs = (struct gpio_regs *)dev_read_addr(dev);
|
|
|
|
platdata->bank_max[0] = dev_read_u32_default(dev,
|
|
"xlnx,gpio-width", 0);
|
|
platdata->bank_input[0] = dev_read_u32_default(dev,
|
|
"xlnx,all-inputs", 0);
|
|
platdata->bank_output[0] = dev_read_u32_default(dev,
|
|
"xlnx,all-outputs", 0);
|
|
|
|
is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
|
|
if (is_dual) {
|
|
platdata->bank_max[1] = dev_read_u32_default(dev,
|
|
"xlnx,gpio2-width", 0);
|
|
platdata->bank_input[1] = dev_read_u32_default(dev,
|
|
"xlnx,all-inputs-2", 0);
|
|
platdata->bank_output[1] = dev_read_u32_default(dev,
|
|
"xlnx,all-outputs-2", 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id xilinx_gpio_ids[] = {
|
|
{ .compatible = "xlnx,xps-gpio-1.00.a",},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(xilinx_gpio) = {
|
|
.name = "xlnx_gpio",
|
|
.id = UCLASS_GPIO,
|
|
.ops = &xilinx_gpio_ops,
|
|
.of_match = xilinx_gpio_ids,
|
|
.ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
|
|
.probe = xilinx_gpio_probe,
|
|
.platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),
|
|
};
|
|
#endif
|