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u-boot/arch/arm/include/asm/arch-tegra20/mc.h
Tom Rini 83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00

35 lines
1.1 KiB
C

/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014
* NVIDIA Corporation <www.nvidia.com>
*/
#ifndef _TEGRA20_MC_H_
#define _TEGRA20_MC_H_
/**
* Defines the memory controller registers we need/care about
*/
struct mc_ctlr {
u32 reserved0[3]; /* offset 0x00 - 0x08 */
u32 mc_emem_cfg; /* offset 0x0C */
u32 mc_emem_adr_cfg; /* offset 0x10 */
u32 mc_emem_arb_cfg0; /* offset 0x14 */
u32 mc_emem_arb_cfg1; /* offset 0x18 */
u32 mc_emem_arb_cfg2; /* offset 0x1C */
u32 reserved1; /* offset 0x20 */
u32 mc_gart_cfg; /* offset 0x24 */
u32 mc_gart_entry_addr; /* offset 0x28 */
u32 mc_gart_entry_data; /* offset 0x2C */
u32 mc_gart_error_req; /* offset 0x30 */
u32 mc_gart_error_addr; /* offset 0x34 */
u32 reserved2; /* offset 0x38 */
u32 mc_timeout_ctrl; /* offset 0x3C */
u32 reserved3[6]; /* offset 0x40 - 0x54 */
u32 mc_decerr_emem_others_status; /* offset 0x58 */
u32 mc_decerr_emem_others_adr; /* offset 0x5C */
u32 reserved4[40]; /* offset 0x60 - 0xFC */
u32 reserved5[93]; /* offset 0x100 - 0x270 */
};
#endif /* _TEGRA20_MC_H_ */