mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 23:02:59 +00:00
6239cc8c4e
Sync all J7200 related v5.11-rc6 Linux kernel dts into U-Boot. MCU R5F nodes are not yet added in Linux kernel yet but were added in U-Boot. In order to avoid regressions, r5f nodes are kept intact. These will be added in kernel in future. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
159 lines
3.7 KiB
Text
159 lines
3.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j7200.dtsi"
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/ {
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memory@80000000 {
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device_type = "memory";
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/* 4G RAM */
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reg = <0x00 0x80000000 0x00 0x80000000>,
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<0x08 0x80000000 0x00 0x80000000>;
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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};
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&wkup_pmx0 {
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mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
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J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
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J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
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J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
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J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
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J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
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J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
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J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
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J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
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J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
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J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
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J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
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J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
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>;
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};
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};
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&main_pmx0 {
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main_i2c0_pins_default: main-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
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J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
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>;
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};
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};
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&hbmc {
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/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
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* appropriate node based on board detection
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*/
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
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ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
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<0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
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flash@0,0 {
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compatible = "cypress,hyperflash", "cfi-flash";
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reg = <0x00 0x00 0x4000000>;
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};
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};
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&mailbox0_cluster0 {
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster1 {
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interrupts = <432>;
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mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster2 {
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status = "disabled";
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};
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&mailbox0_cluster3 {
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status = "disabled";
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};
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&mailbox0_cluster4 {
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status = "disabled";
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};
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&mailbox0_cluster5 {
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status = "disabled";
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};
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&mailbox0_cluster6 {
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status = "disabled";
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};
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&mailbox0_cluster7 {
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status = "disabled";
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};
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&mailbox0_cluster8 {
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status = "disabled";
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};
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&mailbox0_cluster9 {
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status = "disabled";
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};
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&mailbox0_cluster10 {
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status = "disabled";
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};
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&mailbox0_cluster11 {
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status = "disabled";
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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exp_som: gpio@21 {
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compatible = "ti,tca6408";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
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"CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
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"UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
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"GPIO_LIN_EN", "CAN_STB";
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};
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};
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