mirror of
https://github.com/AsahiLinux/u-boot
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20cadbbe2e
Add example configuration stub for the DWC2 USB controller. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Pavel Machek <pavel@denx.de>
216 lines
5.5 KiB
C
216 lines
5.5 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
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#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
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#define CONFIG_SYS_GENERIC_BOARD
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/* Virtual target or real hardware */
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#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_ARMV7
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#define CONFIG_SYS_THUMB_BUILD
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#define CONFIG_SOCFPGA
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/*
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* High level configuration
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*/
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_ARCH_EARLY_INIT_R
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_CLOCKS
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#define CONFIG_FIT
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#define CONFIG_OF_LIBFDT
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#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* Memory configurations
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x0
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
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#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_TEXT_BASE 0x08000040
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#else
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#define CONFIG_SYS_TEXT_BASE 0x01000040
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#endif
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/*
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* U-Boot general configurations
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Print buffer size */
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#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* Boot argument buffer size */
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#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
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#define CONFIG_AUTO_COMPLETE /* Command auto complete */
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#define CONFIG_CMDLINE_EDITING /* Command history etc */
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#define CONFIG_SYS_HUSH_PARSER
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/*
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* Cache
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*/
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#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define CONFIG_SYS_L2_PL310
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#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
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/*
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* Ethernet on SoC (EMAC)
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*/
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#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
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#define CONFIG_DESIGNWARE_ETH
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#define CONFIG_NET_MULTI
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#define CONFIG_DW_ALTDESCRIPTOR
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#define CONFIG_MII
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#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_GIGE
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#endif
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/*
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* FPGA Driver
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*/
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#ifdef CONFIG_CMD_FPGA
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#define CONFIG_FPGA
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#define CONFIG_FPGA_ALTERA
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#define CONFIG_FPGA_SOCFPGA
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#define CONFIG_FPGA_COUNT 1
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#endif
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/*
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* L4 OSC1 Timer 0
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*/
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/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
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#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_TIMER_RATE 2400000
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#else
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#define CONFIG_SYS_TIMER_RATE 25000000
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#endif
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/*
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* L4 Watchdog
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*/
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#ifdef CONFIG_HW_WATCHDOG
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#define CONFIG_DESIGNWARE_WATCHDOG
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#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
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#define CONFIG_DW_WDT_CLOCK_KHZ 25000
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#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000
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#endif
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/*
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* MMC Driver
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*/
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_MMC
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DWMMC
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#define CONFIG_SOCFPGA_DWMMC
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#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
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#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
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#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
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/* FIXME */
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/* using smaller max blk cnt to avoid flooding the limited stack we have */
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
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#endif
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/*
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* Serial Driver
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_NS16550_CLK 1000000
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#else
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#define CONFIG_SYS_NS16550_CLK 100000000
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#endif
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/*
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* USB
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*/
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_DWC2
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#define CONFIG_USB_STORAGE
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/*
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* NOTE: User must define either of the following to select which
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* of the two USB controllers available on SoCFPGA to use.
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* The DWC2 driver doesn't support multiple USB controllers.
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* #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
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* #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
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*/
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#endif
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/*
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* U-Boot environment
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*/
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_ENV_SIZE 4096
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/*
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* SPL
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*
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* SRAM Memory layout:
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*
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* 0xFFFF_0000 ...... Start of SRAM
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* 0xFFFF_xxxx ...... Top of stack (grows down)
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* 0xFFFF_yyyy ...... Malloc area
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* 0xFFFF_zzzz ...... Global Data
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* 0xFFFF_FF00 ...... End of SRAM
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*/
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_RAM_DEVICE
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#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
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#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
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#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
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#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
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#define CONFIG_CRC32_VERIFY
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/* Linker script for SPL */
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#ifdef CONFIG_SPL_BUILD
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#undef CONFIG_PARTITIONS
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#endif
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#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
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