mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-26 13:03:40 +00:00
cf3175bcd8
Since commit c0efc3140e ("ARM: uniphier: change CONFIG_SPL_PAD_TO
to 128KB"), the u-boot.bin should be burned at the offset 0x20000.
I missed to update README.uniphier in that commit. Now updating.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
182 lines
5.1 KiB
Text
182 lines
5.1 KiB
Text
U-Boot for UniPhier SoC family
|
|
==============================
|
|
|
|
|
|
Recommended toolchains
|
|
----------------------
|
|
|
|
The UniPhir platform is well tested with Linaro toolchanis.
|
|
You can download pre-built toolchains from:
|
|
|
|
http://www.linaro.org/downloads/
|
|
|
|
|
|
Compile the source
|
|
------------------
|
|
|
|
sLD3 reference board:
|
|
$ make uniphier_sld3_defconfig
|
|
$ make CROSS_COMPILE=arm-linux-gnueabihf-
|
|
|
|
LD4 reference board:
|
|
$ make uniphier_ld4_sld8_defconfig
|
|
$ make CROSS_COMPILE=arm-linux-gnueabihf-
|
|
|
|
sLD8 reference board:
|
|
$ make uniphier_ld4_sld8_defconfig
|
|
$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-sld8-ref
|
|
|
|
Pro4 reference board:
|
|
$ make uniphier_pro4_defconfig
|
|
$ make CROSS_COMPILE=arm-linux-gnueabihf-
|
|
|
|
Pro4 Ace board:
|
|
$ make uniphier_pro4_defconfig
|
|
$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-ace
|
|
|
|
Pro4 Sanji board:
|
|
$ make uniphier_pro4_defconfig
|
|
$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-sanji
|
|
|
|
Pro5 4KBOX Board:
|
|
$ make uniphier_pxs2_ld6b_defconfig
|
|
$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro5-4kbox
|
|
|
|
PXs2 Gentil board:
|
|
$ make uniphier_pxs2_ld6b_defconfig
|
|
$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-gentil
|
|
|
|
PXs2 Vodka board:
|
|
$ make uniphier_pxs2_ld6b_defconfig
|
|
$ make CROSS_COMPILE=arm-linux-gnueabihf-
|
|
|
|
LD6b reference board:
|
|
$ make uniphier_pxs2_ld6b_defconfig
|
|
$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-ld6b-ref
|
|
|
|
LD11 reference board:
|
|
$ make uniphier_ld11_defconfig
|
|
$ make CROSS_COMPILE=aarch64-linux-gnu-
|
|
|
|
LD20 reference board:
|
|
$ make uniphier_ld20_defconfig
|
|
$ make CROSS_COMPILE=aarch64-linux-gnu-
|
|
|
|
PXs3 reference board:
|
|
$ make uniphier_v8_defconfig
|
|
$ make CROSS_COMPILE=aarch64-linux-gnu- DEVICE_TREE=uniphier-pxs3-ref
|
|
|
|
You may wish to change the "CROSS_COMPILE=..." to use your favorite compiler.
|
|
|
|
|
|
Burn U-Boot images to NAND
|
|
--------------------------
|
|
|
|
Write the following to the NAND device:
|
|
|
|
- spl/u-boot-spl.bin at the offset address 0x00000000
|
|
- u-boot.bin at the offset address 0x00020000
|
|
|
|
or
|
|
|
|
- u-boot-with-spl.bin at the offset address 0x00000000
|
|
|
|
If a TFTP server is available, the images can be easily updated.
|
|
Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
|
|
and then run the following command at the U-Boot command line:
|
|
|
|
=> run nandupdate
|
|
|
|
|
|
Burn U-Boot images to eMMC
|
|
--------------------------
|
|
|
|
Write the following to the Boot partition 1 of the eMMC device:
|
|
|
|
- spl/u-boot-spl.bin at the offset address 0x00000000
|
|
- u-boot.bin at the offset address 0x00020000
|
|
|
|
or
|
|
|
|
- u-boot-with-spl.bin at the offset address 0x00000000
|
|
|
|
If a TFTP server is available, the images can be easily updated.
|
|
Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
|
|
and then run the following command at the U-Boot command line:
|
|
|
|
=> run emmcupdate
|
|
|
|
|
|
UniPhier specific commands
|
|
--------------------------
|
|
|
|
- pinmon (enabled by CONFIG_CMD_PINMON)
|
|
shows the boot mode pins that has been latched at the power-on reset
|
|
|
|
- ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP)
|
|
shows the DDR PHY parameters set by the PHY training
|
|
|
|
- ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP)
|
|
shows the DDR Multi PHY parameters set by the PHY training
|
|
|
|
|
|
Supported devices
|
|
-----------------
|
|
|
|
- UART (on-chip)
|
|
- NAND
|
|
- SD/eMMC
|
|
- USB 2.0 (EHCI)
|
|
- USB 3.0 (xHCI)
|
|
- GPIO
|
|
- LAN (on-board SMSC9118)
|
|
- I2C
|
|
- EEPROM (connected to the on-board I2C bus)
|
|
- Support card (SRAM, NOR flash, some peripherals)
|
|
|
|
|
|
Micro Support Card
|
|
------------------
|
|
|
|
The recommended bit switch settings are as follows:
|
|
|
|
SW2 OFF(1)/ON(0) Description
|
|
------------------------------------------
|
|
bit 1 <---- BKSZ[0]
|
|
bit 2 ----> BKSZ[1]
|
|
bit 3 <---- SoC Bus Width 16/32
|
|
bit 4 <---- SERIAL_SEL[0]
|
|
bit 5 ----> SERIAL_SEL[1]
|
|
bit 6 ----> BOOTSWAP_EN
|
|
bit 7 <---- CS1/CS5
|
|
bit 8 <---- SOC_SERIAL_DISABLE
|
|
|
|
SW8 OFF(1)/ON(0) Description
|
|
------------------------------------------
|
|
bit 1 <---- CS1_SPLIT
|
|
bit 2 <---- CASE9_ON
|
|
bit 3 <---- CASE10_ON
|
|
bit 4 Don't Care Reserve
|
|
bit 5 Don't Care Reserve
|
|
bit 6 Don't Care Reserve
|
|
bit 7 ----> BURST_EN
|
|
bit 8 ----> FLASHBUS32_16
|
|
|
|
The BKSZ[1:0] specifies the address range of memory slot and peripherals
|
|
as follows:
|
|
|
|
BKSZ Description RAM slot Peripherals
|
|
--------------------------------------------------------------------
|
|
0b00 15MB RAM / 1MB Peri 00000000-00efffff 00f00000-00ffffff
|
|
0b01 31MB RAM / 1MB Peri 00000000-01efffff 01f00000-01ffffff
|
|
0b10 64MB RAM / 1MB Peri 00000000-03efffff 03f00000-03ffffff
|
|
0b11 127MB RAM / 1MB Peri 00000000-07efffff 07f00000-07ffffff
|
|
|
|
Set BSKZ[1:0] to 0b01 for U-Boot.
|
|
This mode is the most handy because EA[24] is always supported by the save pin
|
|
mode of the system bus. On the other hand, EA[25] is not supported for some
|
|
newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
|
|
|
|
--
|
|
Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
Jan. 2017
|