mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 23:02:59 +00:00
968597b85c
Add support for USB controller and PHY clocks for QCS404 SoC. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
119 lines
2.8 KiB
C
119 lines
2.8 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* Clock drivers for Qualcomm QCS404
|
|
*
|
|
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <clk-uclass.h>
|
|
#include <dm.h>
|
|
#include <errno.h>
|
|
#include <asm/io.h>
|
|
#include <linux/bitops.h>
|
|
#include "clock-snapdragon.h"
|
|
|
|
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
|
|
|
|
/* GPLL0 clock control registers */
|
|
#define GPLL0_STATUS_ACTIVE BIT(31)
|
|
|
|
static struct vote_clk gcc_blsp1_ahb_clk = {
|
|
.cbcr_reg = BLSP1_AHB_CBCR,
|
|
.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
|
|
.vote_bit = BIT(10) | BIT(5) | BIT(4),
|
|
};
|
|
|
|
static const struct bcr_regs uart2_regs = {
|
|
.cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
|
|
.cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
|
|
.M = BLSP1_UART2_APPS_M,
|
|
.N = BLSP1_UART2_APPS_N,
|
|
.D = BLSP1_UART2_APPS_D,
|
|
};
|
|
|
|
static const struct bcr_regs sdc_regs = {
|
|
.cfg_rcgr = SDCC_CFG_RCGR(1),
|
|
.cmd_rcgr = SDCC_CMD_RCGR(1),
|
|
.M = SDCC_M(1),
|
|
.N = SDCC_N(1),
|
|
.D = SDCC_D(1),
|
|
};
|
|
|
|
static struct pll_vote_clk gpll0_vote_clk = {
|
|
.status = GPLL0_STATUS,
|
|
.status_bit = GPLL0_STATUS_ACTIVE,
|
|
.ena_vote = APCS_GPLL_ENA_VOTE,
|
|
.vote_bit = BIT(0),
|
|
};
|
|
|
|
static const struct bcr_regs usb30_master_regs = {
|
|
.cfg_rcgr = USB30_MASTER_CFG_RCGR,
|
|
.cmd_rcgr = USB30_MASTER_CMD_RCGR,
|
|
.M = USB30_MASTER_M,
|
|
.N = USB30_MASTER_N,
|
|
.D = USB30_MASTER_D,
|
|
};
|
|
|
|
ulong msm_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
|
|
|
switch (clk->id) {
|
|
case GCC_BLSP1_UART2_APPS_CLK:
|
|
/* UART: 115200 */
|
|
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
|
|
CFG_CLK_SRC_CXO);
|
|
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
|
|
break;
|
|
case GCC_BLSP1_AHB_CLK:
|
|
clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
|
|
break;
|
|
case GCC_SDCC1_APPS_CLK:
|
|
/* SDCC1: 200MHz */
|
|
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
|
|
CFG_CLK_SRC_GPLL0);
|
|
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
|
|
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
|
|
break;
|
|
case GCC_SDCC1_AHB_CLK:
|
|
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int msm_enable(struct clk *clk)
|
|
{
|
|
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
|
|
|
switch (clk->id) {
|
|
case GCC_USB30_MASTER_CLK:
|
|
clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
|
|
clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
|
|
CFG_CLK_SRC_GPLL0);
|
|
break;
|
|
case GCC_SYS_NOC_USB3_CLK:
|
|
clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
|
|
break;
|
|
case GCC_USB30_SLEEP_CLK:
|
|
clk_enable_cbc(priv->base + USB30_SLEEP_CBCR);
|
|
break;
|
|
case GCC_USB30_MOCK_UTMI_CLK:
|
|
clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR);
|
|
break;
|
|
case GCC_USB_HS_PHY_CFG_AHB_CLK:
|
|
clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
|
|
break;
|
|
case GCC_USB2A_PHY_SLEEP_CLK:
|
|
clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|