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https://github.com/AsahiLinux/u-boot
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93f26f130e
fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h. To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h. Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
167 lines
3.9 KiB
C
167 lines
3.9 KiB
C
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/types.h>
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#include <asm/io.h>
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#include <asm/fsl_dtsec.h>
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#include <fsl_mdio.h>
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#include <phy.h>
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#include "fm.h"
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#define RCTRL_INIT (RCTRL_GRS | RCTRL_UPROM)
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#define TCTRL_INIT TCTRL_GTS
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#define MACCFG1_INIT MACCFG1_SOFT_RST
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#define MACCFG2_INIT (MACCFG2_PRE_LEN(0x7) | MACCFG2_LEN_CHECK | \
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MACCFG2_PAD_CRC | MACCFG2_FULL_DUPLEX | \
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MACCFG2_IF_MODE_NIBBLE)
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/* MAXFRM - maximum frame length register */
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#define MAXFRM_MASK 0x00003fff
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static void dtsec_init_mac(struct fsl_enet_mac *mac)
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{
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struct dtsec *regs = mac->base;
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/* soft reset */
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out_be32(®s->maccfg1, MACCFG1_SOFT_RST);
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udelay(1000);
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/* clear soft reset, Rx/Tx MAC disable */
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out_be32(®s->maccfg1, 0);
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/* graceful stop rx */
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out_be32(®s->rctrl, RCTRL_INIT);
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udelay(1000);
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/* graceful stop tx */
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out_be32(®s->tctrl, TCTRL_INIT);
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udelay(1000);
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/* disable all interrupts */
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out_be32(®s->imask, IMASK_MASK_ALL);
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/* clear all events */
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out_be32(®s->ievent, IEVENT_CLEAR_ALL);
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/* set the max Rx length */
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out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK);
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/* set the ecntrl to reset value */
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out_be32(®s->ecntrl, ECNTRL_DEFAULT);
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/*
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* Rx length check, no strip CRC for Rx, pad and append CRC for Tx,
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* full duplex
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*/
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out_be32(®s->maccfg2, MACCFG2_INIT);
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}
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static void dtsec_enable_mac(struct fsl_enet_mac *mac)
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{
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struct dtsec *regs = mac->base;
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/* enable Rx/Tx MAC */
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setbits_be32(®s->maccfg1, MACCFG1_RXTX_EN);
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/* clear the graceful Rx stop */
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clrbits_be32(®s->rctrl, RCTRL_GRS);
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/* clear the graceful Tx stop */
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clrbits_be32(®s->tctrl, TCTRL_GTS);
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}
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static void dtsec_disable_mac(struct fsl_enet_mac *mac)
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{
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struct dtsec *regs = mac->base;
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/* graceful Rx stop */
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setbits_be32(®s->rctrl, RCTRL_GRS);
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/* graceful Tx stop */
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setbits_be32(®s->tctrl, TCTRL_GTS);
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/* disable Rx/Tx MAC */
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clrbits_be32(®s->maccfg1, MACCFG1_RXTX_EN);
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}
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static void dtsec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
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{
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struct dtsec *regs = mac->base;
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u32 mac_addr1, mac_addr2;
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/*
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* if a station address of 0x12345678ABCD, perform a write to
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* MACSTNADDR1 of 0xCDAB7856, MACSTNADDR2 of 0x34120000
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*/
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mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
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(mac_addr[3] << 8) | (mac_addr[2]);
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out_be32(®s->macstnaddr1, mac_addr1);
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mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
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out_be32(®s->macstnaddr2, mac_addr2);
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}
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static void dtsec_set_interface_mode(struct fsl_enet_mac *mac,
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phy_interface_t type, int speed)
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{
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struct dtsec *regs = mac->base;
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u32 ecntrl, maccfg2;
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/* clear all bits relative with interface mode */
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ecntrl = in_be32(®s->ecntrl);
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ecntrl &= ~(ECNTRL_TBIM | ECNTRL_GMIIM | ECNTRL_RPM |
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ECNTRL_R100M | ECNTRL_SGMIIM);
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maccfg2 = in_be32(®s->maccfg2);
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maccfg2 &= ~MACCFG2_IF_MODE_MASK;
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if (speed == SPEED_1000)
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maccfg2 |= MACCFG2_IF_MODE_BYTE;
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else
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maccfg2 |= MACCFG2_IF_MODE_NIBBLE;
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/* set interface mode */
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switch (type) {
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case PHY_INTERFACE_MODE_GMII:
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ecntrl |= ECNTRL_GMIIM;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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ecntrl |= (ECNTRL_GMIIM | ECNTRL_RPM);
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if (speed == SPEED_100)
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ecntrl |= ECNTRL_R100M;
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break;
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case PHY_INTERFACE_MODE_RMII:
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if (speed == SPEED_100)
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ecntrl |= ECNTRL_R100M;
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break;
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case PHY_INTERFACE_MODE_SGMII:
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ecntrl |= (ECNTRL_SGMIIM | ECNTRL_TBIM);
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if (speed == SPEED_100)
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ecntrl |= ECNTRL_R100M;
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break;
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default:
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break;
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}
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out_be32(®s->ecntrl, ecntrl);
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out_be32(®s->maccfg2, maccfg2);
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}
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void init_dtsec(struct fsl_enet_mac *mac, void *base,
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void *phyregs, int max_rx_len)
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{
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mac->base = base;
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mac->phyregs = phyregs;
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mac->max_rx_len = max_rx_len;
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mac->init_mac = dtsec_init_mac;
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mac->enable_mac = dtsec_enable_mac;
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mac->disable_mac = dtsec_disable_mac;
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mac->set_mac_addr = dtsec_set_mac_addr;
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mac->set_if_mode = dtsec_set_interface_mode;
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}
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