mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
cae9008f69
With the introduction of the Armada 38x support, its necessary to change the mvneta ethernet driver init call from always 4 times to a configurable value. Lets make this init call more flexible by moving the actually used devices to the config header. Additionally this patch takes care of the slightly different base addresses for the ethernet controllers on A38x. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
116 lines
3.3 KiB
C
116 lines
3.3 KiB
C
/*
|
|
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef _CONFIG_DB_MV7846MP_GP_H
|
|
#define _CONFIG_DB_MV7846MP_GP_H
|
|
|
|
/*
|
|
* High Level Configuration Options (easy to change)
|
|
*/
|
|
#define CONFIG_ARMADA_XP /* SOC Family Name */
|
|
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
|
#define CONFIG_SYS_GENERIC_BOARD
|
|
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
|
|
|
#define CONFIG_SYS_TEXT_BASE 0x04000000
|
|
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
|
|
|
|
/*
|
|
* Commands configuration
|
|
*/
|
|
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
|
#include <config_cmd_default.h>
|
|
#define CONFIG_CMD_DHCP
|
|
#define CONFIG_CMD_ENV
|
|
#define CONFIG_CMD_I2C
|
|
#define CONFIG_CMD_PING
|
|
#define CONFIG_CMD_SF
|
|
#define CONFIG_CMD_SPI
|
|
#define CONFIG_CMD_TFTPPUT
|
|
#define CONFIG_CMD_TIME
|
|
|
|
/* I2C */
|
|
#define CONFIG_SYS_I2C
|
|
#define CONFIG_SYS_I2C_MVTWSI
|
|
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
|
|
#define CONFIG_SYS_I2C_SLAVE 0x0
|
|
#define CONFIG_SYS_I2C_SPEED 100000
|
|
|
|
/* SPI NOR flash default params, used by sf commands */
|
|
#define CONFIG_SF_DEFAULT_SPEED 1000000
|
|
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
|
|
#define CONFIG_SPI_FLASH_STMICRO
|
|
#define CONFIG_SPI_FLASH_SPANSION
|
|
#define CONFIG_SPI_FLASH_BAR
|
|
|
|
/* Environment in SPI NOR flash */
|
|
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
|
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
|
|
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
|
|
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
|
|
|
|
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
|
|
#define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 }
|
|
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
|
|
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
|
#define CONFIG_RESET_PHY_R
|
|
|
|
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
|
|
#define CONFIG_SYS_ALT_MEMTEST
|
|
|
|
/*
|
|
* mv-common.h should be defined after CMD configs since it used them
|
|
* to enable certain macros
|
|
*/
|
|
#include "mv-common.h"
|
|
|
|
/*
|
|
* Memory layout while starting into the bin_hdr via the
|
|
* BootROM:
|
|
*
|
|
* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
|
|
* 0x4000.4030 bin_hdr start address
|
|
* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
|
|
* 0x4007.fffc BootROM stack top
|
|
*
|
|
* The address space between 0x4007.fffc and 0x400f.fff is not locked in
|
|
* L2 cache thus cannot be used.
|
|
*/
|
|
|
|
/* SPL */
|
|
/* Defines for SPL */
|
|
#define CONFIG_SPL_FRAMEWORK
|
|
#define CONFIG_SPL_TEXT_BASE 0x40004030
|
|
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
|
|
|
|
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
|
|
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
|
|
|
|
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
|
|
CONFIG_SPL_BSS_MAX_SIZE)
|
|
#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
|
|
|
|
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
|
|
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
|
|
|
|
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
|
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
|
#define CONFIG_SPL_SERIAL_SUPPORT
|
|
#define CONFIG_SPL_I2C_SUPPORT
|
|
|
|
/* SPL related SPI defines */
|
|
#define CONFIG_SPL_SPI_SUPPORT
|
|
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
|
#define CONFIG_SPL_SPI_LOAD
|
|
#define CONFIG_SPL_SPI_BUS 0
|
|
#define CONFIG_SPL_SPI_CS 0
|
|
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
|
|
|
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
|
|
#define CONFIG_SYS_MVEBU_DDR
|
|
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
|
|
|
|
#endif /* _CONFIG_DB_MV7846MP_GP_H */
|