mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
137 lines
5.6 KiB
C
137 lines
5.6 KiB
C
/*
|
|
* (C) Copyright 2003, 2004
|
|
* ARM Ltd.
|
|
* Philippe Robin, <philippe.robin@arm.com>
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
/*
|
|
* ARM PrimeCell UART's (PL010 & PL011)
|
|
* ------------------------------------
|
|
*
|
|
* Definitions common to both PL010 & PL011
|
|
*
|
|
*/
|
|
#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */
|
|
#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */
|
|
#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */
|
|
#define UART_PL01x_FR 0x18 /* Flag register (Read only). */
|
|
|
|
#define UART_PL01x_RSR_OE 0x08
|
|
#define UART_PL01x_RSR_BE 0x04
|
|
#define UART_PL01x_RSR_PE 0x02
|
|
#define UART_PL01x_RSR_FE 0x01
|
|
|
|
#define UART_PL01x_FR_TXFE 0x80
|
|
#define UART_PL01x_FR_RXFF 0x40
|
|
#define UART_PL01x_FR_TXFF 0x20
|
|
#define UART_PL01x_FR_RXFE 0x10
|
|
#define UART_PL01x_FR_BUSY 0x08
|
|
#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
|
|
|
|
/*
|
|
* PL010 definitions
|
|
*
|
|
*/
|
|
#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */
|
|
#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */
|
|
#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */
|
|
#define UART_PL010_CR 0x14 /* Control register. */
|
|
#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */
|
|
#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */
|
|
#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */
|
|
|
|
#define UART_PL010_CR_LPE (1 << 7)
|
|
#define UART_PL010_CR_RTIE (1 << 6)
|
|
#define UART_PL010_CR_TIE (1 << 5)
|
|
#define UART_PL010_CR_RIE (1 << 4)
|
|
#define UART_PL010_CR_MSIE (1 << 3)
|
|
#define UART_PL010_CR_IIRLP (1 << 2)
|
|
#define UART_PL010_CR_SIREN (1 << 1)
|
|
#define UART_PL010_CR_UARTEN (1 << 0)
|
|
|
|
#define UART_PL010_LCRH_WLEN_8 (3 << 5)
|
|
#define UART_PL010_LCRH_WLEN_7 (2 << 5)
|
|
#define UART_PL010_LCRH_WLEN_6 (1 << 5)
|
|
#define UART_PL010_LCRH_WLEN_5 (0 << 5)
|
|
#define UART_PL010_LCRH_FEN (1 << 4)
|
|
#define UART_PL010_LCRH_STP2 (1 << 3)
|
|
#define UART_PL010_LCRH_EPS (1 << 2)
|
|
#define UART_PL010_LCRH_PEN (1 << 1)
|
|
#define UART_PL010_LCRH_BRK (1 << 0)
|
|
|
|
|
|
#define UART_PL010_BAUD_460800 1
|
|
#define UART_PL010_BAUD_230400 3
|
|
#define UART_PL010_BAUD_115200 7
|
|
#define UART_PL010_BAUD_57600 15
|
|
#define UART_PL010_BAUD_38400 23
|
|
#define UART_PL010_BAUD_19200 47
|
|
#define UART_PL010_BAUD_14400 63
|
|
#define UART_PL010_BAUD_9600 95
|
|
#define UART_PL010_BAUD_4800 191
|
|
#define UART_PL010_BAUD_2400 383
|
|
#define UART_PL010_BAUD_1200 767
|
|
/*
|
|
* PL011 definitions
|
|
*
|
|
*/
|
|
#define UART_PL011_IBRD 0x24
|
|
#define UART_PL011_FBRD 0x28
|
|
#define UART_PL011_LCRH 0x2C
|
|
#define UART_PL011_CR 0x30
|
|
#define UART_PL011_IMSC 0x38
|
|
#define UART_PL011_PERIPH_ID0 0xFE0
|
|
|
|
#define UART_PL011_LCRH_SPS (1 << 7)
|
|
#define UART_PL011_LCRH_WLEN_8 (3 << 5)
|
|
#define UART_PL011_LCRH_WLEN_7 (2 << 5)
|
|
#define UART_PL011_LCRH_WLEN_6 (1 << 5)
|
|
#define UART_PL011_LCRH_WLEN_5 (0 << 5)
|
|
#define UART_PL011_LCRH_FEN (1 << 4)
|
|
#define UART_PL011_LCRH_STP2 (1 << 3)
|
|
#define UART_PL011_LCRH_EPS (1 << 2)
|
|
#define UART_PL011_LCRH_PEN (1 << 1)
|
|
#define UART_PL011_LCRH_BRK (1 << 0)
|
|
|
|
#define UART_PL011_CR_CTSEN (1 << 15)
|
|
#define UART_PL011_CR_RTSEN (1 << 14)
|
|
#define UART_PL011_CR_OUT2 (1 << 13)
|
|
#define UART_PL011_CR_OUT1 (1 << 12)
|
|
#define UART_PL011_CR_RTS (1 << 11)
|
|
#define UART_PL011_CR_DTR (1 << 10)
|
|
#define UART_PL011_CR_RXE (1 << 9)
|
|
#define UART_PL011_CR_TXE (1 << 8)
|
|
#define UART_PL011_CR_LPE (1 << 7)
|
|
#define UART_PL011_CR_IIRLP (1 << 2)
|
|
#define UART_PL011_CR_SIREN (1 << 1)
|
|
#define UART_PL011_CR_UARTEN (1 << 0)
|
|
|
|
#define UART_PL011_IMSC_OEIM (1 << 10)
|
|
#define UART_PL011_IMSC_BEIM (1 << 9)
|
|
#define UART_PL011_IMSC_PEIM (1 << 8)
|
|
#define UART_PL011_IMSC_FEIM (1 << 7)
|
|
#define UART_PL011_IMSC_RTIM (1 << 6)
|
|
#define UART_PL011_IMSC_TXIM (1 << 5)
|
|
#define UART_PL011_IMSC_RXIM (1 << 4)
|
|
#define UART_PL011_IMSC_DSRMIM (1 << 3)
|
|
#define UART_PL011_IMSC_DCDMIM (1 << 2)
|
|
#define UART_PL011_IMSC_CTSMIM (1 << 1)
|
|
#define UART_PL011_IMSC_RIMIM (1 << 0)
|