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https://github.com/AsahiLinux/u-boot
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65e25bea59
In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
210 lines
5.1 KiB
C
210 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Broadcom.
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*/
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#include <common.h>
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gic.h>
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#include <asm/gic-v3.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/sizes.h>
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static u32 lpi_id_bits;
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#define LPI_NRBITS lpi_id_bits
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#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
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#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
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/* Number of GIC re-distributors */
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#define MAX_GIC_REDISTRIBUTORS 8
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/*
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* gic_v3_its_priv - gic details
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*
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* @gicd_base: gicd base address
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* @gicr_base: gicr base address
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* @lpi_base: gic lpi base address
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* @num_redist: number of gic re-distributors
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*/
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struct gic_v3_its_priv {
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ulong gicd_base;
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ulong gicr_base;
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ulong lpi_base;
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u32 num_redist;
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};
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static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
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{
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struct udevice *dev;
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fdt_addr_t addr;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_IRQ,
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DM_DRIVER_GET(arm_gic_v3_its), &dev);
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if (ret) {
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pr_err("%s: failed to get %s irq device\n", __func__,
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DM_DRIVER_GET(arm_gic_v3_its)->name);
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return ret;
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}
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addr = dev_read_addr_index(dev, 0);
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if (addr == FDT_ADDR_T_NONE) {
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pr_err("%s: failed to get GICD address\n", __func__);
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return -EINVAL;
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}
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priv->gicd_base = addr;
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addr = dev_read_addr_index(dev, 1);
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if (addr == FDT_ADDR_T_NONE) {
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pr_err("%s: failed to get GICR address\n", __func__);
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return -EINVAL;
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}
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priv->gicr_base = addr;
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return 0;
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}
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static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
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{
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struct regmap *regmap;
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_SYSCON,
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DM_DRIVER_GET(gic_lpi_syscon), &dev);
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if (ret) {
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pr_err("%s: failed to get %s syscon device\n", __func__,
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DM_DRIVER_GET(gic_lpi_syscon)->name);
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return ret;
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}
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regmap = syscon_get_regmap(dev);
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if (!regmap) {
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pr_err("%s: failed to regmap for %s syscon device\n", __func__,
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DM_DRIVER_GET(gic_lpi_syscon)->name);
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return -ENODEV;
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}
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priv->lpi_base = regmap->ranges[0].start;
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priv->num_redist = dev_read_u32_default(dev, "max-gic-redistributors",
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MAX_GIC_REDISTRIBUTORS);
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return 0;
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}
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/*
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* Program the GIC LPI configuration tables for all
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* the re-distributors and enable the LPI table
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*/
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int gic_lpi_tables_init(void)
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{
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struct gic_v3_its_priv priv;
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u32 gicd_typer;
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u64 val;
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u64 tmp;
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int i;
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u64 redist_lpi_base;
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u64 pend_base;
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if (gic_v3_its_get_gic_addr(&priv))
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return -EINVAL;
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if (gic_v3_its_get_gic_lpi_addr(&priv))
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return -EINVAL;
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gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
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/* GIC support for Locality specific peripheral interrupts (LPI's) */
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if (!(gicd_typer & GICD_TYPER_LPIS)) {
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pr_err("GIC implementation does not support LPI's\n");
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return -EINVAL;
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}
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/*
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* Check for LPI is disabled for all the redistributors.
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* Once the LPI table is enabled, can not program the
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* LPI configuration tables again, unless the GIC is reset.
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*/
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for (i = 0; i < priv.num_redist; i++) {
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u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
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if ((readl((uintptr_t)(priv.gicr_base + offset))) &
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GICR_CTLR_ENABLE_LPIS) {
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pr_err("Re-Distributor %d LPI is already enabled\n",
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i);
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return -EINVAL;
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}
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}
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/* lpi_id_bits to get LPI_PENDBASE_SZ and LPi_PROPBASE_SZ */
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lpi_id_bits = min_t(u32, GICD_TYPER_ID_BITS(gicd_typer),
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ITS_MAX_LPI_NRBITS);
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/* Set PropBase */
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val = (priv.lpi_base |
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GICR_PROPBASER_INNERSHAREABLE |
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GICR_PROPBASER_RAWAWB |
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((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
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writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
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tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
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if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
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if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
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val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
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GICR_PROPBASER_CACHEABILITY_MASK);
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val |= GICR_PROPBASER_NC;
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writeq(val,
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(uintptr_t)(priv.gicr_base + GICR_PROPBASER));
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}
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}
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redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ;
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pend_base = priv.gicr_base + GICR_PENDBASER;
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for (i = 0; i < priv.num_redist; i++) {
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u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
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val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
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GICR_PENDBASER_INNERSHAREABLE |
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GICR_PENDBASER_RAWAWB);
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writeq(val, (uintptr_t)(pend_base + offset));
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tmp = readq((uintptr_t)(pend_base + offset));
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if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
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val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
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GICR_PENDBASER_CACHEABILITY_MASK);
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val |= GICR_PENDBASER_NC;
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writeq(val, (uintptr_t)(pend_base + offset));
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}
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/* Enable LPI for the redistributor */
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writel(GICR_CTLR_ENABLE_LPIS,
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(uintptr_t)(priv.gicr_base + offset));
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}
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return 0;
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}
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static const struct udevice_id gic_v3_its_ids[] = {
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{ .compatible = "arm,gic-v3" },
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{}
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};
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U_BOOT_DRIVER(arm_gic_v3_its) = {
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.name = "gic-v3",
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.id = UCLASS_IRQ,
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.of_match = gic_v3_its_ids,
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};
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static const struct udevice_id gic_lpi_syscon_ids[] = {
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{ .compatible = "gic-lpi-base" },
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{}
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};
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U_BOOT_DRIVER(gic_lpi_syscon) = {
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.name = "gic-lpi-base",
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.id = UCLASS_SYSCON,
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.of_match = gic_lpi_syscon_ids,
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};
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