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The hardware DQS gate training is a bit unreliable and does not always find the best delay settings. So we introduce a 32-bit 'dqs_gating_delay' variable, where each byte encodes the DQS gating delay for each byte lane. The delay granularity is 1/4 cycle. Also we allow to enable the active DQS gating window mode, which works better than the passive mode in practice. The DDR3 spec says that there is a 0.9 cycles preamble and 0.3 cycle postamble. The DQS window has to be opened during preamble and closed during postamble. In the passive window mode, the gating window is opened and closed by just using the gating delay settings. And because of the 1/4 cycle delay granularity, accurately hitting the 0.3 cycle long postamble is a bit tough. In the active window mode, the gating window is auto-closing with the help of monitoring the DQS line, which relaxes the gating delay accuracy requirements. But the hardware DQS gate training is still performed in the passive window mode. It is a more strict test, which is reducing the results variance compared to the training with active window mode. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
185 lines
6.4 KiB
C
185 lines
6.4 KiB
C
/*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Berg Xing <bergxing@allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Sunxi platform dram register definition.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_DRAM_H
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#define _SUNXI_DRAM_H
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#include <linux/types.h>
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struct sunxi_dram_reg {
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u32 ccr; /* 0x00 controller configuration register */
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u32 dcr; /* 0x04 dram configuration register */
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u32 iocr; /* 0x08 i/o configuration register */
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u32 csr; /* 0x0c controller status register */
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u32 drr; /* 0x10 dram refresh register */
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u32 tpr0; /* 0x14 dram timing parameters register 0 */
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u32 tpr1; /* 0x18 dram timing parameters register 1 */
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u32 tpr2; /* 0x1c dram timing parameters register 2 */
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u32 gdllcr; /* 0x20 global dll control register */
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u8 res0[0x28];
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u32 rslr0; /* 0x4c rank system latency register */
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u32 rslr1; /* 0x50 rank system latency register */
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u8 res1[0x8];
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u32 rdgr0; /* 0x5c rank dqs gating register */
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u32 rdgr1; /* 0x60 rank dqs gating register */
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u8 res2[0x34];
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u32 odtcr; /* 0x98 odt configuration register */
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u32 dtr0; /* 0x9c data training register 0 */
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u32 dtr1; /* 0xa0 data training register 1 */
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u32 dtar; /* 0xa4 data training address register */
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u32 zqcr0; /* 0xa8 zq control register 0 */
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u32 zqcr1; /* 0xac zq control register 1 */
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u32 zqsr; /* 0xb0 zq status register */
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u32 idcr; /* 0xb4 initializaton delay configure reg */
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u8 res3[0x138];
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u32 mr; /* 0x1f0 mode register */
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u32 emr; /* 0x1f4 extended mode register */
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u32 emr2; /* 0x1f8 extended mode register */
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u32 emr3; /* 0x1fc extended mode register */
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u32 dllctr; /* 0x200 dll control register */
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u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */
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/* 0x208 dll control register 1(byte 1) */
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/* 0x20c dll control register 2(byte 2) */
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/* 0x210 dll control register 3(byte 3) */
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/* 0x214 dll control register 4(byte 4) */
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u32 dqtr0; /* 0x218 dq timing register */
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u32 dqtr1; /* 0x21c dq timing register */
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u32 dqtr2; /* 0x220 dq timing register */
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u32 dqtr3; /* 0x224 dq timing register */
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u32 dqstr; /* 0x228 dqs timing register */
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u32 dqsbtr; /* 0x22c dqsb timing register */
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u32 mcr; /* 0x230 mode configure register */
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u8 res[0x8];
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u32 ppwrsctl; /* 0x23c pad power save control */
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u32 apr; /* 0x240 arbiter period register */
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u32 pldtr; /* 0x244 priority level data threshold reg */
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u8 res5[0x8];
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u32 hpcr[32]; /* 0x250 host port configure register */
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u8 res6[0x10];
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u32 csel; /* 0x2e0 controller select register */
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};
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struct dram_para {
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u32 clock;
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u32 mbus_clock;
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u32 type;
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u32 rank_num;
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u32 density;
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u32 io_width;
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u32 bus_width;
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u32 cas;
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u32 zq;
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u32 odt_en;
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u32 size;
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u32 tpr0;
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u32 tpr1;
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u32 tpr2;
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u32 tpr3;
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u32 tpr4;
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u32 tpr5;
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u32 emr1;
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u32 emr2;
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u32 emr3;
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u32 dqs_gating_delay;
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u32 active_windowing;
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};
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#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
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#define DRAM_CCR_DQS_GATE (0x1 << 14)
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#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
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#define DRAM_CCR_ITM_OFF (0x1 << 28)
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#define DRAM_CCR_DATA_TRAINING (0x1 << 30)
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#define DRAM_CCR_INIT (0x1 << 31)
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#define DRAM_MEMORY_TYPE_DDR1 1
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#define DRAM_MEMORY_TYPE_DDR2 2
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#define DRAM_MEMORY_TYPE_DDR3 3
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#define DRAM_MEMORY_TYPE_LPDDR2 4
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#define DRAM_MEMORY_TYPE_LPDDR 5
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#define DRAM_DCR_TYPE (0x1 << 0)
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#define DRAM_DCR_TYPE_DDR2 0x0
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#define DRAM_DCR_TYPE_DDR3 0x1
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#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
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#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
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#define DRAM_DCR_IO_WIDTH_8BIT 0x0
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#define DRAM_DCR_IO_WIDTH_16BIT 0x1
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#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
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#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
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#define DRAM_DCR_CHIP_DENSITY_256M 0x0
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#define DRAM_DCR_CHIP_DENSITY_512M 0x1
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#define DRAM_DCR_CHIP_DENSITY_1024M 0x2
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#define DRAM_DCR_CHIP_DENSITY_2048M 0x3
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#define DRAM_DCR_CHIP_DENSITY_4096M 0x4
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#define DRAM_DCR_CHIP_DENSITY_8192M 0x5
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#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
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#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
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#define DRAM_DCR_BUS_WIDTH_32BIT 0x3
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#define DRAM_DCR_BUS_WIDTH_16BIT 0x1
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#define DRAM_DCR_BUS_WIDTH_8BIT 0x0
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#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
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#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
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#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
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#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
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#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
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#define DRAM_DCR_MODE_SEQ 0x0
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#define DRAM_DCR_MODE_INTERLEAVE 0x1
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#define DRAM_CSR_DTERR (0x1 << 20)
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#define DRAM_CSR_DTIERR (0x1 << 21)
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#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
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#define DRAM_DRR_TRFC(n) ((n) & 0xff)
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#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
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#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24)
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#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
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#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
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#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
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#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
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#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
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#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
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#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
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#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
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#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
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#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
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#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
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#define DRAM_MCR_RESET (0x1 << 12)
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#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
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#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
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#define DRAM_MCR_DCLK_OUT (0x1 << 16)
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#define DRAM_DLLCR_NRESET (0x1 << 30)
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#define DRAM_DLLCR_DISABLE (0x1 << 31)
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#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
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#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
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#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */
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#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */
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#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */
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#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0)
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#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
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#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
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#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
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#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
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#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
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#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
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#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
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#define DRAM_MR_POWER_DOWN (0x1 << 12)
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#define DRAM_CSEL_MAGIC 0x16237495
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unsigned long sunxi_dram_init(void);
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unsigned long dramc_init(struct dram_para *para);
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#endif /* _SUNXI_DRAM_H */
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