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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
36 lines
943 B
C
36 lines
943 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2015 Xilinx, Inc,
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* Michal Simek <michal.simek@amd.com>
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*/
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#ifndef _ZYNQMPPL_H_
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#define _ZYNQMPPL_H_
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#include <xilinx.h>
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#include <linux/bitops.h>
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#define ZYNQMP_FPGA_OP_INIT (1 << 0)
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#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
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#define ZYNQMP_FPGA_OP_DONE (1 << 2)
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#define ZYNQMP_FPGA_FLAG_AUTHENTICATED BIT(2)
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#define ZYNQMP_FPGA_FLAG_ENCRYPTED BIT(3)
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#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
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#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \
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ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
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#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
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#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
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extern struct xilinx_fpga_op zynqmp_op;
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#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
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#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY | \
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FPGA_XILINX_ZYNQMP_DDRAUTH | \
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FPGA_XILINX_ZYNQMP_ENC)
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#else
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#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY)
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#endif
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#endif /* _ZYNQMPPL_H_ */
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