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https://github.com/AsahiLinux/u-boot
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13f1c44bc5
We do not need to check for EMIF_GCLK and L3_GCLK being active. This was a hold-over from bringup and no longer required. Signed-off-by: Tom Rini <trini@ti.com>
311 lines
8 KiB
C
311 lines
8 KiB
C
/*
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* clock.c
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*
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* clocks for AM33XX based boards
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#define PRCM_MOD_EN 0x2
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#define PRCM_FORCE_WAKEUP 0x2
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#define PRCM_FUNCTL 0x0
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#define PRCM_EMIF_CLK_ACTIVITY BIT(2)
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#define PRCM_L3_GCLK_ACTIVITY BIT(4)
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#define PLL_BYPASS_MODE 0x4
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#define ST_MN_BYPASS 0x00000100
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#define ST_DPLL_CLK 0x00000001
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#define CLK_SEL_MASK 0x7ffff
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#define CLK_DIV_MASK 0x1f
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#define CLK_DIV2_MASK 0x7f
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#define CLK_SEL_SHIFT 0x8
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#define CLK_MODE_SEL 0x7
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#define CLK_MODE_MASK 0xfffffff8
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#define CLK_DIV_SEL 0xFFFFFFE0
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#define CPGMAC0_IDLE 0x30000
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const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
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const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
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const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
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static void enable_interface_clocks(void)
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{
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/* Enable all the Interconnect Modules */
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writel(PRCM_MOD_EN, &cmper->l3clkctrl);
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while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
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while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
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while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
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while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
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while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
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while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
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while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
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;
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}
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/*
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* Force power domain wake up transition
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* Ensure that the corresponding interface clock is active before
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* using the peripheral
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*/
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static void power_domain_wkup_transition(void)
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{
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writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
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writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
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writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
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writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
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writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
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}
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/*
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* Enable the peripheral clock for required peripherals
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*/
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static void enable_per_clocks(void)
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{
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/* Enable the control module though RBL would have done it*/
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writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
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while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
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;
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/* Enable the module clock */
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writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
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while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
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;
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/* Select the Master osc 24 MHZ as Timer2 clock source */
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writel(0x1, &cmdpll->clktimer2clk);
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/* UART0 */
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writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
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while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
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;
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/* MMC0*/
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writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
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while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
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;
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/* i2c0 */
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writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
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while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
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;
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/* gpio1 module */
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writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
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while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
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;
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/* gpio2 module */
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writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
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while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
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;
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/* gpio3 module */
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writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
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while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
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;
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/* i2c1 */
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writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
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while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
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;
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/* Ethernet */
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writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
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while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
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;
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}
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static void mpu_pll_config(void)
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{
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u32 clkmode, clksel, div_m2;
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clkmode = readl(&cmwkup->clkmoddpllmpu);
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clksel = readl(&cmwkup->clkseldpllmpu);
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div_m2 = readl(&cmwkup->divm2dpllmpu);
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/* Set the PLL to bypass Mode */
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writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
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while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
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writel(clksel, &cmwkup->clkseldpllmpu);
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div_m2 = div_m2 & ~CLK_DIV_MASK;
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div_m2 = div_m2 | MPUPLL_M2;
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writel(div_m2, &cmwkup->divm2dpllmpu);
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clkmode = clkmode | CLK_MODE_SEL;
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writel(clkmode, &cmwkup->clkmoddpllmpu);
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while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
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;
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}
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static void core_pll_config(void)
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{
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u32 clkmode, clksel, div_m4, div_m5, div_m6;
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clkmode = readl(&cmwkup->clkmoddpllcore);
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clksel = readl(&cmwkup->clkseldpllcore);
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div_m4 = readl(&cmwkup->divm4dpllcore);
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div_m5 = readl(&cmwkup->divm5dpllcore);
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div_m6 = readl(&cmwkup->divm6dpllcore);
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/* Set the PLL to bypass Mode */
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writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
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while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
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writel(clksel, &cmwkup->clkseldpllcore);
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div_m4 = div_m4 & ~CLK_DIV_MASK;
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div_m4 = div_m4 | COREPLL_M4;
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writel(div_m4, &cmwkup->divm4dpllcore);
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div_m5 = div_m5 & ~CLK_DIV_MASK;
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div_m5 = div_m5 | COREPLL_M5;
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writel(div_m5, &cmwkup->divm5dpllcore);
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div_m6 = div_m6 & ~CLK_DIV_MASK;
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div_m6 = div_m6 | COREPLL_M6;
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writel(div_m6, &cmwkup->divm6dpllcore);
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clkmode = clkmode | CLK_MODE_SEL;
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writel(clkmode, &cmwkup->clkmoddpllcore);
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while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
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;
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}
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static void per_pll_config(void)
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{
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u32 clkmode, clksel, div_m2;
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clkmode = readl(&cmwkup->clkmoddpllper);
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clksel = readl(&cmwkup->clkseldpllper);
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div_m2 = readl(&cmwkup->divm2dpllper);
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/* Set the PLL to bypass Mode */
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writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
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while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
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writel(clksel, &cmwkup->clkseldpllper);
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div_m2 = div_m2 & ~CLK_DIV2_MASK;
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div_m2 = div_m2 | PERPLL_M2;
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writel(div_m2, &cmwkup->divm2dpllper);
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clkmode = clkmode | CLK_MODE_SEL;
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writel(clkmode, &cmwkup->clkmoddpllper);
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while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
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;
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}
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static void ddr_pll_config(void)
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{
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u32 clkmode, clksel, div_m2;
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clkmode = readl(&cmwkup->clkmoddpllddr);
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clksel = readl(&cmwkup->clkseldpllddr);
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div_m2 = readl(&cmwkup->divm2dpllddr);
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/* Set the PLL to bypass Mode */
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clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
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writel(clkmode, &cmwkup->clkmoddpllddr);
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/* Wait till bypass mode is enabled */
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while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
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!= ST_MN_BYPASS)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
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writel(clksel, &cmwkup->clkseldpllddr);
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div_m2 = div_m2 & CLK_DIV_SEL;
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div_m2 = div_m2 | DDRPLL_M2;
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writel(div_m2, &cmwkup->divm2dpllddr);
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clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
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writel(clkmode, &cmwkup->clkmoddpllddr);
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/* Wait till dpll is locked */
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while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
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;
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}
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void enable_emif_clocks(void)
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{
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/* Enable the EMIF_FW Functional clock */
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writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
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/* Enable EMIF0 Clock */
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writel(PRCM_MOD_EN, &cmper->emifclkctrl);
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/* Poll if module is functional */
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while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
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;
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}
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/*
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* Configure the PLL/PRCM for necessary peripherals
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*/
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void pll_init()
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{
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mpu_pll_config();
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core_pll_config();
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per_pll_config();
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ddr_pll_config();
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/* Enable the required interconnect clocks */
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enable_interface_clocks();
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/* Power domain wake up transition */
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power_domain_wkup_transition();
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/* Enable the required peripherals */
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enable_per_clocks();
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}
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