u-boot/board/keymile/kmp204x/ddr.c
Valentin Longchamp 877bfe37dc mpc85xx: introduce the kmp204x reference design support
This patch introduces the support for Keymile's kmp204x reference
design. This design is based on Freescale's P2040/P2041 SoC.

The peripherals used by this design are:
- DDR3 RAM with SPD support
- SPI NOR Flash as boot medium
- NAND Flash
- 2 PCIe busses (hosts 1 and 3)
- 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5)
- 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt
  FPGA
- 2 HW I2C busses
- last but not least, the mandatory serial port

The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb
support and was changed according to our design (that means essentially
removing what is not present on the designs and a few adaptations).

There is currently only one prototype board that is based on this design
and this patch also introduces it. The board is called kmlion1.

Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

kmp204x: update the ENV #define

The comments had to be refined as well as the total size

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix ddr.c]
Acked-by: York Sun <yorksun@freescale.com>
2013-10-24 09:36:26 -07:00

64 lines
1.5 KiB
C

/*
* (C) Copyright 2013 Keymile AG
* Valentin Longchamp <valentin.longchamp@keymile.com>
*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
if (ctrl_num) {
printf("Wrong parameter for controller number %d", ctrl_num);
return;
}
/* automatic calibration for nb of cycles between read and DQS pre */
popts->cpo_override = 0xFF;
/* 1/2 clk delay between wr command and data strobe */
popts->write_data_delay = 4;
/* clk lauched 1/2 applied cylcle after address command */
popts->clk_adjust = 4;
/* 1T timing: command/address held for only 1 cycle */
popts->twot_en = 0;
/* we have only one module, half str should be OK */
popts->half_strength_driver_enable = 1;
/* wrlvl values overriden as recommended by ddr init func */
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
popts->wrlvl_start = 0x6;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
puts("Initializing with SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
debug(" DDR: ");
return dram_size;
}