u-boot/board/freescale/imx8ulp_evk
Ye Li 8b956bdddd imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
M33 will be the TRDC owner and needs to configure TRDC. A35 is the
XRDC owner, ATF will configure XRDC.

The handshake between U-boot and M33 image is used to sync TRDC and
XRDC configuration completion. Once the handshake is done, A35 and M33
can access the allowed resources in others domain.

The handshake is needed when M33 is booted or DBD_EN fused, because both
cases will enable the TRDC. If handshake is timeout, the boot will hang.
We use SIM GPR0 to pass the info from SPL to u-boot, because before the
handshake, u-boot can't access SEC SIM and FSB.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29 20:15:42 +02:00
..
ddr_init.c
imx8ulp_evk.c imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion 2023-03-29 20:15:42 +02:00
Kconfig nxp: Make board/freescale/common/Kconfig safe to include once in arch/Kconfig 2022-07-05 17:03:02 -04:00
lpddr4_timing.c imx: imx8ulp_evk: Update LPDDR4 PHY settings 2022-04-12 17:33:57 +02:00
lpddr4_timing_266.c imx: imx8ulp: add ND/LD clock 2022-04-12 17:33:56 +02:00
MAINTAINERS
Makefile imx: imx8ulp: add ND/LD clock 2022-04-12 17:33:56 +02:00
spl.c imx: imx8ulp: Get chip revision from Sentinel 2023-03-29 20:15:41 +02:00