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https://github.com/AsahiLinux/u-boot
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01f573eb88
Sync all am642-evm/am642-sk related DT files with Linux v6.5-rc1. - drop timer1 in favor of main_timer0 in am64-main.dtsi. Need to delete clock & power domain properties of main_timer1 in -r5.dts else won't boot. This is because timer_init is done during rproc_start to start System Firmware, but we can't do any clock/power-domain operations before System Firmware starts. - same constraint applies to main_uart0 - drop cpsw3g custom DT property 'mac_efuse' and custom DT node cpsw-phy-sel as driver picks these from standard property/node. - include board dts file in -r5 dts file to avoid duplication of nodes. Include -u-boot.dtsi on top. - drop duplicate nodes in -r5 dts and -u-boot.dtsi Signed-off-by: Roger Quadros <rogerq@kernel.org> Tested-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
66 lines
1.2 KiB
Text
66 lines
1.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM642 SoC family in Dual core configuration
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*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-am64.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0: cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x40000>;
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cache-line-size = <64>;
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cache-sets = <256>;
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};
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};
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