mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 14:23:00 +00:00
6c43f6c8d9
All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
495 lines
14 KiB
C
495 lines
14 KiB
C
/*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/xusb-padctl.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
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struct tegra_xusb_phy_ops {
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int (*prepare)(struct tegra_xusb_phy *phy);
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int (*enable)(struct tegra_xusb_phy *phy);
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int (*disable)(struct tegra_xusb_phy *phy);
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int (*unprepare)(struct tegra_xusb_phy *phy);
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};
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struct tegra_xusb_phy {
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const struct tegra_xusb_phy_ops *ops;
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struct tegra_xusb_padctl *padctl;
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};
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struct tegra_xusb_padctl {
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struct fdt_resource regs;
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unsigned int enable;
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struct tegra_xusb_phy phys[2];
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};
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static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
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unsigned long offset)
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{
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u32 value = readl(padctl->regs.start + offset);
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debug("padctl: %08lx > %08x\n", offset, value);
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return value;
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}
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static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
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u32 value, unsigned long offset)
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{
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debug("padctl: %08lx < %08x\n", offset, value);
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writel(value, padctl->regs.start + offset);
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}
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#define XUSB_PADCTL_ELPG_PROGRAM 0x024
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
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static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
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{
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u32 value;
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if (padctl->enable++ > 0)
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return 0;
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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return 0;
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}
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static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
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{
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u32 value;
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if (padctl->enable == 0) {
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error("unbalanced enable/disable");
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return 0;
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}
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if (--padctl->enable > 0)
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return 0;
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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return 0;
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}
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static int phy_prepare(struct tegra_xusb_phy *phy)
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{
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int err;
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err = tegra_xusb_padctl_enable(phy->padctl);
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if (err < 0)
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return err;
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reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
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return 0;
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}
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static int phy_unprepare(struct tegra_xusb_phy *phy)
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{
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reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
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return tegra_xusb_padctl_disable(phy->padctl);
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}
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
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#define CLK_RST_XUSBIO_PLL_CFG0 0x51c
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#define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
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#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
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#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
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#define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
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#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
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static int pcie_phy_enable(struct tegra_xusb_phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy->padctl;
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unsigned long start;
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u32 value;
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debug("> %s(phy=%p)\n", __func__, phy);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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udelay(1);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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debug(" waiting for calibration\n");
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start = get_timer(0);
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while (get_timer(start) < 250) {
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
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break;
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}
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debug(" done\n");
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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debug(" waiting for calibration to stop\n");
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start = get_timer(0);
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while (get_timer(start) < 250) {
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
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break;
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}
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debug(" done\n");
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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debug(" waiting for PLL to lock...\n");
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start = get_timer(0);
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while (get_timer(start) < 250) {
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
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break;
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}
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debug(" done\n");
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
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value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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debug(" waiting for register calibration...\n");
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start = get_timer(0);
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while (get_timer(start) < 250) {
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
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break;
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}
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debug(" done\n");
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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debug(" waiting for register calibration to stop...\n");
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start = get_timer(0);
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while (get_timer(start) < 250) {
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
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break;
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}
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debug(" done\n");
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
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value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
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value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
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value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
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value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
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writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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udelay(1);
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value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
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value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
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writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
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debug("< %s()\n", __func__);
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return 0;
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}
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static int pcie_phy_disable(struct tegra_xusb_phy *phy)
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{
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return 0;
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}
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static const struct tegra_xusb_phy_ops pcie_phy_ops = {
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.prepare = phy_prepare,
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.enable = pcie_phy_enable,
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.disable = pcie_phy_disable,
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.unprepare = phy_unprepare,
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};
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static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
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.phys = {
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[0] = {
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.ops = &pcie_phy_ops,
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},
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},
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};
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static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
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const void *fdt, int node)
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{
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int err;
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err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
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if (err < 0) {
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error("registers not found");
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return err;
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}
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debug("regs: %pa-%pa\n", &padctl->regs.start,
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&padctl->regs.end);
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return 0;
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}
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static int process_nodes(const void *fdt, int nodes[], unsigned int count)
|
|
{
|
|
unsigned int i;
|
|
int err;
|
|
|
|
debug("> %s(fdt=%p, nodes=%p, count=%u)\n", __func__, fdt, nodes,
|
|
count);
|
|
|
|
for (i = 0; i < count; i++) {
|
|
enum fdt_compat_id id;
|
|
|
|
if (!fdtdec_get_is_enabled(fdt, nodes[i]))
|
|
continue;
|
|
|
|
id = fdtdec_lookup(fdt, nodes[i]);
|
|
switch (id) {
|
|
case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
|
|
case COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL:
|
|
break;
|
|
|
|
default:
|
|
error("unsupported compatible: %s",
|
|
fdtdec_get_compatible(id));
|
|
continue;
|
|
}
|
|
|
|
err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
|
|
if (err < 0) {
|
|
error("failed to parse DT: %d",
|
|
err);
|
|
continue;
|
|
}
|
|
|
|
/* deassert XUSB padctl reset */
|
|
reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
|
|
|
|
/* only a single instance is supported */
|
|
break;
|
|
}
|
|
|
|
debug("< %s()\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
|
|
{
|
|
struct tegra_xusb_phy *phy = NULL;
|
|
|
|
switch (type) {
|
|
case TEGRA_XUSB_PADCTL_PCIE:
|
|
phy = &padctl->phys[0];
|
|
phy->padctl = padctl;
|
|
break;
|
|
}
|
|
|
|
return phy;
|
|
}
|
|
|
|
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
|
|
{
|
|
if (phy && phy->ops && phy->ops->prepare)
|
|
return phy->ops->prepare(phy);
|
|
|
|
return phy ? -ENOSYS : -EINVAL;
|
|
}
|
|
|
|
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
|
|
{
|
|
if (phy && phy->ops && phy->ops->enable)
|
|
return phy->ops->enable(phy);
|
|
|
|
return phy ? -ENOSYS : -EINVAL;
|
|
}
|
|
|
|
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
|
|
{
|
|
if (phy && phy->ops && phy->ops->disable)
|
|
return phy->ops->disable(phy);
|
|
|
|
return phy ? -ENOSYS : -EINVAL;
|
|
}
|
|
|
|
int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
|
|
{
|
|
if (phy && phy->ops && phy->ops->unprepare)
|
|
return phy->ops->unprepare(phy);
|
|
|
|
return phy ? -ENOSYS : -EINVAL;
|
|
}
|
|
|
|
void tegra_xusb_padctl_init(const void *fdt)
|
|
{
|
|
int count, nodes[1];
|
|
|
|
debug("> %s(fdt=%p)\n", __func__, fdt);
|
|
|
|
count = fdtdec_find_aliases_for_id(fdt, "padctl",
|
|
COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
|
|
nodes, ARRAY_SIZE(nodes));
|
|
if (process_nodes(fdt, nodes, count))
|
|
return;
|
|
|
|
count = fdtdec_find_aliases_for_id(fdt, "padctl",
|
|
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
|
|
nodes, ARRAY_SIZE(nodes));
|
|
if (process_nodes(fdt, nodes, count))
|
|
return;
|
|
|
|
debug("< %s()\n", __func__);
|
|
}
|