mirror of
https://github.com/AsahiLinux/u-boot
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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
103 lines
2.3 KiB
C
103 lines
2.3 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <miiphy.h>
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#include <wait_bit.h>
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#include <linux/bitops.h>
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#include "mscc_miim.h"
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#define MIIM_STATUS 0x0
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#define MIIM_STAT_BUSY BIT(3)
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#define MIIM_CMD 0x8
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#define MIIM_CMD_SCAN BIT(0)
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#define MIIM_CMD_OPR_WRITE BIT(1)
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#define MIIM_CMD_OPR_READ BIT(2)
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#define MIIM_CMD_SINGLE_SCAN BIT(3)
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#define MIIM_CMD_WRDATA(x) ((x) << 4)
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#define MIIM_CMD_REGAD(x) ((x) << 20)
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#define MIIM_CMD_PHYAD(x) ((x) << 25)
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#define MIIM_CMD_VLD BIT(31)
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#define MIIM_DATA 0xC
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#define MIIM_DATA_ERROR (0x2 << 16)
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static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
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{
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return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
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false, 250, false);
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}
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int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
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u32 val;
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int ret;
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ret = mscc_miim_wait_ready(miim);
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if (ret)
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goto out;
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writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
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MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
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miim->regs + MIIM_CMD);
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ret = mscc_miim_wait_ready(miim);
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if (ret)
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goto out;
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val = readl(miim->regs + MIIM_DATA);
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if (val & MIIM_DATA_ERROR) {
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ret = -EIO;
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goto out;
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}
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ret = val & 0xFFFF;
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out:
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return ret;
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}
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int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
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int ret;
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ret = mscc_miim_wait_ready(miim);
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if (ret < 0)
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goto out;
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writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
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MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
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MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
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out:
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return ret;
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}
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struct mii_dev *mscc_mdiobus_init(struct mscc_miim_dev *miim, int *miim_count,
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phys_addr_t miim_base,
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unsigned long miim_size)
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{
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struct mii_dev *bus;
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bus = mdio_alloc();
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if (!bus)
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return NULL;
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*miim_count += 1;
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sprintf(bus->name, "miim-bus%d", *miim_count);
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miim[*miim_count].regs = ioremap(miim_base, miim_size);
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miim[*miim_count].miim_base = miim_base;
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miim[*miim_count].miim_size = miim_size;
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bus->priv = &miim[*miim_count];
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bus->read = mscc_miim_read;
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bus->write = mscc_miim_write;
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if (mdio_register(bus))
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return NULL;
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miim[*miim_count].bus = bus;
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return bus;
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}
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