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Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de> |
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.. | ||
config.h | ||
cpu.h | ||
efuse.h | ||
gpio.h | ||
soc.h |