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cf946c6d09
Since there are lots of difference between kirkwood and armada series, it is better to seperate them but still keep the most common file shared by all marvell platform in the mv-common configure file. This patch move the kirkwood only driver definitoin in mv-common to the <soc_name>/config.h. This patch is tested with compilation for armada100 and guruplug. Signed-off-by: Lei Wen <leiwen@marvell.com>
145 lines
4.4 KiB
C
145 lines
4.4 KiB
C
/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/*
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* This file should be included in board config header file.
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*
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* It supports common definitions for Kirkwood platform
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*/
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#ifndef _KW_CONFIG_H
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#define _KW_CONFIG_H
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#if defined (CONFIG_KW88F6281)
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#include <asm/arch/kw88f6281.h>
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#elif defined (CONFIG_KW88F6192)
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#include <asm/arch/kw88f6192.h>
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#else
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#error "SOC Name not defined"
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#endif /* CONFIG_KW88F6281 */
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#define CONFIG_ARM926EJS 1 /* Basic Architecture */
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#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
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#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
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#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
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#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
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/*
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* By default kwbimage.cfg from board specific folder is used
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* If for some board, different configuration file need to be used,
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* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
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*/
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#ifndef CONFIG_SYS_KWD_CONFIG
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#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
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#endif /* CONFIG_SYS_KWD_CONFIG */
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/* Kirkwood has 2k of Security SRAM, use it for SP */
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#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
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#define CONFIG_NR_DRAM_BANKS_MAX 2
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#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
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#define MV_UART_CONSOLE_BASE KW_UART0_BASE
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#define MV_SATA_BASE KW_SATA_BASE
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#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
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#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
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/*
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* NAND configuration
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*/
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_KIRKWOOD
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#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
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#define NAND_ALLOW_ERASE_ALL 1
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#endif
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/*
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* SPI Flash configuration
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*/
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#ifdef CONFIG_CMD_SF
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#define CONFIG_HARD_SPI 1
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#define CONFIG_KIRKWOOD_SPI 1
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */
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#endif
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/*
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* Ethernet Driver configuration
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*/
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#ifdef CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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#define CONFIG_NET_MULTI /* specify more that one ports available */
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#define CONFIG_MII /* expose smi ove miiphy interface */
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#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
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#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
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#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
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#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
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#endif /* CONFIG_CMD_NET */
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/*
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* USB/EHCI
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*/
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_EHCI_KIRKWOOD
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#define CONFIG_EHCI_IS_TDI
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#endif /* CONFIG_CMD_USB */
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/*
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* IDE Support on SATA ports
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*/
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#ifdef CONFIG_CMD_IDE
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#define __io
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#define CONFIG_CMD_EXT2
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#define CONFIG_MVSATA_IDE
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#define CONFIG_IDE_PREINIT
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#define CONFIG_MVSATA_IDE_USE_PORT1
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/* Needs byte-swapping for ATA data register */
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#define CONFIG_IDE_SWAP_IO
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/* Data, registers and alternate blocks are at the same offset */
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
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#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
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/* Each 8-bit ATA register is aligned to a 4-bytes address */
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#define CONFIG_SYS_ATA_STRIDE 4
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/* Controller supports 48-bits LBA addressing */
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#define CONFIG_LBA48
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/* CONFIG_CMD_IDE requires some #defines for ATA registers */
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#define CONFIG_SYS_IDE_MAXBUS 2
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#define CONFIG_SYS_IDE_MAXDEVICE 2
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/* ATA registers base is at SATA controller base */
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#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
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#endif /* CONFIG_CMD_IDE */
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/*
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* I2C related stuff
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*/
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#ifdef CONFIG_CMD_I2C
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#define CONFIG_I2C_MVTWSI
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif
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#endif /* _KW_CONFIG_H */
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