u-boot/doc/device-tree-bindings/memory-controllers/st,stm32-fmc.txt
Patrick Delaunay 3a29afcbbf doc: binding: rename directory ram to memory-controller
Alignment with kernel directory name as it have already bindings for
DDR controllers in the directory:
Documentation/devicetree/bindings/memory-controller

PS: the drivers using RAM u-class should be associated with
    this binding directory

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-28 14:21:46 -05:00

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ST, stm32 flexible memory controller Drive
Required properties:
- compatible : "st,stm32-fmc"
- reg : fmc controller base address
- clocks : fmc controller clock
u-boot,dm-pre-reloc: flag to initialize memory before relocation.
on-board sdram memory attributes:
- st,sdram-control : parameters for sdram configuration, in this order:
number of columns
number of rows
memory width
number of intenal banks in memory
cas latency
read burst enable or disable
read pipe delay
- st,sdram-timing: timings for sdram, in this order:
tmrd
txsr
tras
trc
trp
trcd
There is device tree include file at :
include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
parameters as MACROS.
Example:
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
clocks = <&rcc 0 64>;
u-boot,dm-pre-reloc;
};
&fmc {
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
status = "okay";
/* sdram memory configuration from sdram datasheet */
bank1: bank@0 {
st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
TRCD_18>;
};
/* sdram memory configuration from sdram datasheet */
bank2: bank@1 {
st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
TRCD_18>;
};
}