mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-23 16:11:54 +00:00
ce00370b87
Copy the devicetree source for the H6 SoC and all existing boards from the Linux v5.18-rc1 tag. To maintain ABI compatibility with existing LTS kernels, one change moving some IP blocks to the r_intc interrupt controller is excluded. This effectively reverts Linux commits 189bef235dd3 and 73088dfee635. This commit also adds the following new board devicetrees: - sun50i-h6-pine-h64-model-b.dts - sun50i-h6-tanix-tx6-mini.dts This update should not impact any existing U-Boot functionality. Signed-off-by: Samuel Holland <samuel@sholland.org>
117 lines
3.1 KiB
Text
117 lines
3.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
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// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
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/ {
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cpu_opp_table: opp-table-cpu {
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compatible = "allwinner,sun50i-h6-operating-points";
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nvmem-cells = <&cpu_speed_grade>;
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opp-shared;
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opp-480000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt-speed0 = <880000 880000 1200000>;
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opp-microvolt-speed1 = <820000 820000 1200000>;
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opp-microvolt-speed2 = <820000 820000 1200000>;
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};
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opp-720000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt-speed0 = <880000 880000 1200000>;
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opp-microvolt-speed1 = <820000 820000 1200000>;
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opp-microvolt-speed2 = <820000 820000 1200000>;
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};
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opp-816000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt-speed0 = <880000 880000 1200000>;
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opp-microvolt-speed1 = <820000 820000 1200000>;
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opp-microvolt-speed2 = <820000 820000 1200000>;
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};
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opp-888000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <888000000>;
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opp-microvolt-speed0 = <880000 880000 1200000>;
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opp-microvolt-speed1 = <820000 820000 1200000>;
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opp-microvolt-speed2 = <820000 820000 1200000>;
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};
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opp-1080000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1080000000>;
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opp-microvolt-speed0 = <940000 940000 1200000>;
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opp-microvolt-speed1 = <880000 880000 1200000>;
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opp-microvolt-speed2 = <880000 880000 1200000>;
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};
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opp-1320000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1320000000>;
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opp-microvolt-speed0 = <1000000 1000000 1200000>;
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opp-microvolt-speed1 = <940000 940000 1200000>;
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opp-microvolt-speed2 = <940000 940000 1200000>;
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};
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opp-1488000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1488000000>;
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opp-microvolt-speed0 = <1060000 1060000 1200000>;
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opp-microvolt-speed1 = <1000000 1000000 1200000>;
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opp-microvolt-speed2 = <1000000 1000000 1200000>;
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};
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opp-1608000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt-speed0 = <1090000 1090000 1200000>;
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opp-microvolt-speed1 = <1030000 1030000 1200000>;
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opp-microvolt-speed2 = <1030000 1030000 1200000>;
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};
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opp-1704000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1704000000>;
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opp-microvolt-speed0 = <1120000 1120000 1200000>;
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opp-microvolt-speed1 = <1060000 1060000 1200000>;
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opp-microvolt-speed2 = <1060000 1060000 1200000>;
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};
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opp-1800000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt-speed0 = <1160000 1160000 1200000>;
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opp-microvolt-speed1 = <1100000 1100000 1200000>;
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opp-microvolt-speed2 = <1100000 1100000 1200000>;
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};
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};
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};
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&cpu0 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&cpu1 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&cpu2 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&cpu3 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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