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9539738509
Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
110 lines
2.6 KiB
C
110 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <linux/bitops.h>
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#include "pinctrl-rockchip.h"
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static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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u8 bit;
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u32 data;
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regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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? priv->regmap_pmu : priv->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3036_PULL_OFFSET 0x118
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#define RK3036_PULL_PINS_PER_REG 16
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#define RK3036_PULL_BANK_STRIDE 8
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static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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*reg = RK3036_PULL_OFFSET;
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*reg += bank->bank_num * RK3036_PULL_BANK_STRIDE;
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*reg += (pin_num / RK3036_PULL_PINS_PER_REG) * 4;
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*bit = pin_num % RK3036_PULL_PINS_PER_REG;
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};
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static int rk3036_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit;
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u32 data;
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if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
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pull != PIN_CONFIG_BIAS_DISABLE)
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return -ENOTSUPP;
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rk3036_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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data = BIT(bit + 16);
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if (pull == PIN_CONFIG_BIAS_DISABLE)
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data |= BIT(bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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static struct rockchip_pin_bank rk3036_pin_banks[] = {
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PIN_BANK(0, 32, "gpio0"),
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PIN_BANK(1, 32, "gpio1"),
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PIN_BANK(2, 32, "gpio2"),
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};
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static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
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.pin_banks = rk3036_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
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.grf_mux_offset = 0xa8,
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.set_mux = rk3036_set_mux,
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.set_pull = rk3036_set_pull,
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};
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static const struct udevice_id rk3036_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3036-pinctrl",
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.data = (ulong)&rk3036_pin_ctrl
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},
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{}
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};
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U_BOOT_DRIVER(pinctrl_rockchip) = {
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.name = "rk3036-pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3036_pinctrl_ids,
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.priv_auto = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if CONFIG_IS_ENABLED(OF_REAL)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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