mirror of
https://github.com/AsahiLinux/u-boot
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fe2f284270
The offset of the current read back register is the value of the gpio pin,
not the value written for the gpio output.
This patch fix it to avoid the other gpio output value controlled by the
same register being set incorrectly.
Fixes: 7ad889b0f3 ("gpio: Add Aspeed GPIO driver")
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
299 lines
7.2 KiB
C
299 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2015 IBM Corp.
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* Joel Stanley <joel@jms.id.au>
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* Ryan Chen <ryan_chen@aspeedtech.com>
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*
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* Implementation extracted from the Linux kernel and adapted for u-boot.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <config.h>
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <linux/bug.h>
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#include <linux/sizes.h>
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struct aspeed_gpio_priv {
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void *regs;
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};
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struct aspeed_gpio_bank {
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u16 val_regs; /* +0: Rd: read input value, Wr: set write latch
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* +4: Rd/Wr: Direction (0=in, 1=out)
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*/
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u16 rdata_reg; /* Rd: read write latch, Wr: <none> */
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u16 irq_regs;
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u16 debounce_regs;
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u16 tolerance_regs;
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u16 cmdsrc_regs;
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const char names[4][3];
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};
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static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
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{
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.val_regs = 0x0000,
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.rdata_reg = 0x00c0,
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.irq_regs = 0x0008,
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.debounce_regs = 0x0040,
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.tolerance_regs = 0x001c,
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.cmdsrc_regs = 0x0060,
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.names = { "A", "B", "C", "D" },
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},
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{
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.val_regs = 0x0020,
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.rdata_reg = 0x00c4,
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.irq_regs = 0x0028,
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.debounce_regs = 0x0048,
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.tolerance_regs = 0x003c,
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.cmdsrc_regs = 0x0068,
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.names = { "E", "F", "G", "H" },
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},
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{
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.val_regs = 0x0070,
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.rdata_reg = 0x00c8,
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.irq_regs = 0x0098,
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.debounce_regs = 0x00b0,
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.tolerance_regs = 0x00ac,
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.cmdsrc_regs = 0x0090,
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.names = { "I", "J", "K", "L" },
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},
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{
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.val_regs = 0x0078,
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.rdata_reg = 0x00cc,
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.irq_regs = 0x00e8,
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.debounce_regs = 0x0100,
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.tolerance_regs = 0x00fc,
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.cmdsrc_regs = 0x00e0,
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.names = { "M", "N", "O", "P" },
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},
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{
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.val_regs = 0x0080,
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.rdata_reg = 0x00d0,
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.irq_regs = 0x0118,
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.debounce_regs = 0x0130,
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.tolerance_regs = 0x012c,
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.cmdsrc_regs = 0x0110,
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.names = { "Q", "R", "S", "T" },
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},
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{
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.val_regs = 0x0088,
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.rdata_reg = 0x00d4,
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.irq_regs = 0x0148,
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.debounce_regs = 0x0160,
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.tolerance_regs = 0x015c,
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.cmdsrc_regs = 0x0140,
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.names = { "U", "V", "W", "X" },
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},
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{
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.val_regs = 0x01E0,
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.rdata_reg = 0x00d8,
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.irq_regs = 0x0178,
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.debounce_regs = 0x0190,
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.tolerance_regs = 0x018c,
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.cmdsrc_regs = 0x0170,
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.names = { "Y", "Z", "AA", "AB" },
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},
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{
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.val_regs = 0x01e8,
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.rdata_reg = 0x00dc,
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.irq_regs = 0x01a8,
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.debounce_regs = 0x01c0,
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.tolerance_regs = 0x01bc,
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.cmdsrc_regs = 0x01a0,
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.names = { "AC", "", "", "" },
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},
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};
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enum aspeed_gpio_reg {
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reg_val,
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reg_rdata,
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reg_dir,
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reg_irq_enable,
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reg_irq_type0,
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reg_irq_type1,
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reg_irq_type2,
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reg_irq_status,
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reg_debounce_sel1,
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reg_debounce_sel2,
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reg_tolerance,
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reg_cmdsrc0,
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reg_cmdsrc1,
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};
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#define GPIO_VAL_VALUE 0x00
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#define GPIO_VAL_DIR 0x04
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#define GPIO_IRQ_ENABLE 0x00
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#define GPIO_IRQ_TYPE0 0x04
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#define GPIO_IRQ_TYPE1 0x08
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#define GPIO_IRQ_TYPE2 0x0c
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#define GPIO_IRQ_STATUS 0x10
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#define GPIO_DEBOUNCE_SEL1 0x00
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#define GPIO_DEBOUNCE_SEL2 0x04
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#define GPIO_CMDSRC_0 0x00
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#define GPIO_CMDSRC_1 0x04
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#define GPIO_CMDSRC_ARM 0
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#define GPIO_CMDSRC_LPC 1
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#define GPIO_CMDSRC_COLDFIRE 2
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#define GPIO_CMDSRC_RESERVED 3
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/* This will be resolved at compile time */
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static inline void __iomem *bank_reg(struct aspeed_gpio_priv *gpio,
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const struct aspeed_gpio_bank *bank,
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const enum aspeed_gpio_reg reg)
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{
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switch (reg) {
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case reg_val:
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return gpio->regs + bank->val_regs + GPIO_VAL_VALUE;
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case reg_rdata:
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return gpio->regs + bank->rdata_reg;
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case reg_dir:
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return gpio->regs + bank->val_regs + GPIO_VAL_DIR;
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case reg_irq_enable:
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return gpio->regs + bank->irq_regs + GPIO_IRQ_ENABLE;
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case reg_irq_type0:
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return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE0;
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case reg_irq_type1:
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return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE1;
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case reg_irq_type2:
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return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE2;
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case reg_irq_status:
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return gpio->regs + bank->irq_regs + GPIO_IRQ_STATUS;
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case reg_debounce_sel1:
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return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
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case reg_debounce_sel2:
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return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
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case reg_tolerance:
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return gpio->regs + bank->tolerance_regs;
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case reg_cmdsrc0:
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return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_0;
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case reg_cmdsrc1:
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return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_1;
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}
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BUG();
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}
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#define GPIO_BANK(x) ((x) >> 5)
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#define GPIO_OFFSET(x) ((x) & 0x1f)
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#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
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static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
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{
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unsigned int bank = GPIO_BANK(offset);
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WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
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return &aspeed_gpio_banks[bank];
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}
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static int
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aspeed_gpio_direction_input(struct udevice *dev, unsigned int offset)
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{
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struct aspeed_gpio_priv *priv = dev_get_priv(dev);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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u32 dir = readl(bank_reg(priv, bank, reg_dir));
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dir &= ~GPIO_BIT(offset);
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writel(dir, bank_reg(priv, bank, reg_dir));
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return 0;
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}
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static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset,
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int value)
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{
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struct aspeed_gpio_priv *priv = dev_get_priv(dev);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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u32 dir = readl(bank_reg(priv, bank, reg_dir));
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u32 output = readl(bank_reg(priv, bank, reg_rdata));
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dir |= GPIO_BIT(offset);
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writel(dir, bank_reg(priv, bank, reg_dir));
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if (value)
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output |= GPIO_BIT(offset);
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else
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output &= ~GPIO_BIT(offset);
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writel(output, bank_reg(priv, bank, reg_val));
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return 0;
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}
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static int aspeed_gpio_get_value(struct udevice *dev, unsigned int offset)
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{
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struct aspeed_gpio_priv *priv = dev_get_priv(dev);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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return !!(readl(bank_reg(priv, bank, reg_val)) & GPIO_BIT(offset));
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}
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static int
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aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value)
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{
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struct aspeed_gpio_priv *priv = dev_get_priv(dev);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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u32 data = readl(bank_reg(priv, bank, reg_rdata));
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if (value)
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data |= GPIO_BIT(offset);
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else
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data &= ~GPIO_BIT(offset);
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writel(data, bank_reg(priv, bank, reg_val));
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return 0;
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}
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static int aspeed_gpio_get_function(struct udevice *dev, unsigned int offset)
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{
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struct aspeed_gpio_priv *priv = dev_get_priv(dev);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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if (readl(bank_reg(priv, bank, reg_dir)) & GPIO_BIT(offset))
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return GPIOF_OUTPUT;
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return GPIOF_INPUT;
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}
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static const struct dm_gpio_ops aspeed_gpio_ops = {
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.direction_input = aspeed_gpio_direction_input,
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.direction_output = aspeed_gpio_direction_output,
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.get_value = aspeed_gpio_get_value,
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.set_value = aspeed_gpio_set_value,
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.get_function = aspeed_gpio_get_function,
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};
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static int aspeed_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct aspeed_gpio_priv *priv = dev_get_priv(dev);
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uc_priv->bank_name = dev->name;
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ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count);
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priv->regs = devfdt_get_addr_ptr(dev);
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return 0;
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}
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static const struct udevice_id aspeed_gpio_ids[] = {
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{ .compatible = "aspeed,ast2400-gpio", },
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{ .compatible = "aspeed,ast2500-gpio", },
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{ .compatible = "aspeed,ast2600-gpio", },
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{ }
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};
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U_BOOT_DRIVER(gpio_aspeed) = {
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.name = "gpio-aspeed",
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.id = UCLASS_GPIO,
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.of_match = aspeed_gpio_ids,
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.ops = &aspeed_gpio_ops,
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.probe = aspeed_gpio_probe,
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.priv_auto = sizeof(struct aspeed_gpio_priv),
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};
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