mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
2395625209
The GW74xx is based on the i.MX 8M Plus SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- PCIe Gen 3.0 switch (build option)
- USB 3.0 HUB
- USB Type-C front panel connector
- GPS
- 3-axis accelerometer
- CAN bus
- 6x GbE RJ45 front-panel jacks
- 1x IMX8M FEC RGMII GbE (with Passive PoE)
- 5x IMX8M EQOS RGMII 6 port GbE Switch
(1x with 802.3af class 5 Active PoE)
- RS232/RS485/RS422 serial transceiver
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- DigI/O header (UART/GPIO/I2C/ADC)
- 802.11ac WiFi
- Bluetooth BLE
- 3x MiniPCIe sockets with PCI/USB
- 1x M.2 Socket with USB2.0, PCIe, and dual-SIM
- PMIC
- Wide range DC input supply (8V to 60V DC)
Do the following to add support for this and future imx8mp-venice boards:
- add dts
- add DRAM config
- add PMIC config
- add IMX8MP support in spl.c and venice.c
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
185 lines
2.6 KiB
Text
185 lines
2.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Gateworks Corporation
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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u-boot,dm-spl;
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wdt = <&wdog1>;
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};
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};
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&eqos {
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ assigned-clock-rates;
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};
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ðphy0 {
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reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
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reset-delay-us = <1000>;
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reset-post-delay-us = <300000>;
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};
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&fec {
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phy-reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <15>;
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phy-reset-post-delay = <100>;
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};
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&gpio1 {
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u-boot,dm-spl;
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dio0_hog {
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gpio-hog;
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input;
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gpios = <9 GPIO_ACTIVE_LOW>;
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line-name = "dio0";
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};
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dio1_hog {
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gpio-hog;
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input;
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gpios = <11 GPIO_ACTIVE_LOW>;
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line-name = "dio1";
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};
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};
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&gpio2 {
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u-boot,dm-spl;
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pcie1_wdis_hog {
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gpio-hog;
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gpios = <17 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "pcie1_wdis#";
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};
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pcie2_wdis_hog {
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gpio-hog;
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gpios = <18 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "pcie2_wdis#";
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};
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pcie3_wdis_hog {
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gpio-hog;
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gpios = <14 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "pcie3_wdis#";
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};
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};
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&gpio3 {
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u-boot,dm-spl;
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m2_dis2_hog {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "m2_gdis#";
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};
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m2rst_hog {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "m2_rst#";
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};
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m2_off_hog {
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gpio-hog;
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gpios = <14 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "m2_off#";
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};
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};
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&gpio4 {
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u-boot,dm-spl;
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m2_dis1_hog {
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gpio-hog;
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gpios = <18 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "m2_wdis#";
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};
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uart_rs485_hog {
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gpio-hog;
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gpios = <31 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "uart_rs485";
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};
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};
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&gpio5 {
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u-boot,dm-spl;
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uart_half_hog {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "uart_half";
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};
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uart_term_hog {
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "uart_term";
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};
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};
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&i2c1 {
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u-boot,dm-spl;
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};
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&i2c2 {
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u-boot,dm-spl;
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};
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&i2c3 {
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u-boot,dm-spl;
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};
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&pinctrl_i2c1 {
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u-boot,dm-spl;
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};
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&pinctrl_wdog {
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u-boot,dm-spl;
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};
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&usdhc2 {
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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assigned-clock-rates = <400000000>;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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sd-uhs-ddr50;
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sd-uhs-sdr104;
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u-boot,dm-spl;
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};
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&usdhc3 {
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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assigned-clock-rates = <400000000>;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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u-boot,dm-spl;
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};
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&wdog1 {
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u-boot,dm-spl;
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};
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